Aryan Gupta

Junior Undergraduate aryan.gupta@iitgn.ac.in

Discipline of Electrical Engineering +91 8899290407
Indian Institute of Technology, Gandhinagar

ACADEMIC DETAILS

Degree Specialization Institute Year CPI/%

B.Tech. Electrical Engineering IIT Gandhinagar 2020-Present 8.80
Class XII Physics, Chemistry, Maths KC Public School, Jammu 2019-2020 97.8
Class X KC Public School, Jammu 2017-2018 97.3
INTERNSHIPS
• Digital Design Intern, Texas Instruments [May’23-July’23]
(Mentor - Mr. Satish Sajjanar, Supervisor - Mr. Pervez Garg)
◦ Developed Python scripts for an ATPG Live Coverage Dashboard, interfacing with Cadence Modus, to provide
real-time chip partition-level coverage during diverse test modes, enhancing fault detection.
◦ Designed and implemented a dynamic database within the dashboard, capturing fault metrics (eg. fault type, fault
status) for SOC faults, updated automatically post each Modus test mode commit.
• Summer Research Intern Programme, IIT Gandhinagar [May’22-July’22]
(Mentor - Mr. Tom Glint, Supervisor - Prof. Joycee Mekie)
◦ Enhanced Simba ML hardware architecture by implementing a specialized posit-based number system, tailored for
efficient data representation in DNNs.
◦ Utilized Timeloop-Accelergy to demonstrate system-level advantages across prominent neural networks like ResNet-
18, VGG-16, and VGG-19
PROJECTS
• Digital Bit-Parallel IMC for ML applications [Jan’23 - April’23]
(Prof. Joycee Mekie, IIT Gandhinagar)
◦ Reviewed an IEEE paper and implemented the proposed 6T SRAM-based digital compute in memory (CIM) macro
to support various computations with reconfigurable bit precision. The architecture is based on BL Computing with
a short WL pulse followed by BL Boosting to enhance the memory operation frequency while avoiding compute
disturb issues.
• Scripting and Automation [Feb’23]
(Mr. Kailash Prasad, IIT Gandhinagar)
◦ Designed an Automatic Library Evaluation Framework that automates the synthesis flow of the Xilinx Vivado and
Cadence Genus Tool. The script takes Verilog files as input, performs synthesis, generates the area, power, and delay
reports and combines them all in a CSV file
• A 6T SRAM Based Two Dimensional PUF [Sept’22 - Nov’22]
(Prof. Joycee Mekie, IIT Gandhinagar)
◦ Reviewed an IEEE paper and implemented the proposed 2-dimensional programmable SRAM-based PUF having
split wordlines with vertical and horizontal connections. The bit-lines are placed orthogonally to generate one-bit
data with four cells enriching the entropy source to 24 transistors. Performed 1000 point Monte Carlo Simulations
and ran the NIST tests to check the PUF for its uniqueness, reliability and randomness.

TECHNICAL SKILLS
• Programming Languages: Python,TCL,Verilog,SystemVerilog,Perl.
• Tools: MATLAB, Xilinx Vivado, Cadence Virtuoso, Cadence Genus, Cadence Innovus, Cadence Modus.
• Relevant Courses: Digital Systems(10/10), VLSI Design(10/10), IC Design(10/10).
ACHIEVEMENTS
• Felicitated with Dean’s List award in Semester 6 for excellent academic performance(10.2 SPI), IITGN.
• Secured an exceptional A+ grade (11/10) in two core courses Control Systems and Communication Systems, underscoring
exceptional subject proficiency.
• Winner of HackRuch’22 in Hardware domain (Annual Coding Hackathon of IITGN) FPGAworks: A Capture the Flag
event designed around Programmable Hardware Development.
PUBLICATIONS
• Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers. 28th Asia and South Pacific
Design Automation Conference, Nominated for Best paper Award.
• Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA, 2023 IEEE International Sym-
posium on Performance Analysis of Systems and Software.
POSITIONS OF RESPONSIBILITY
• Secretary, Hardware, IoT and VLSI Hobby Group, IIT Gandhinagar [Aug’22 - Present]
• ADH (Academic Discussion Hour) Mentor for ES203: Digital Systems, IIT Gandhinagar [Aug’22 - Nov’22]