DEPARTMENT OF ELECTRONICS &

TELECOMMUNICATION VIVEKANAND EDUCATION

SOCIETY’S
INSTITUTE OF TECHNOLOGY
UNIVERSITY OF MUMBAI
2018-2019

Report on

2D multiplier using VHDL

Digital VLSI

TE Electronics & Telecommunication

Semester VI

Submitted by

Pratik Pathak-51
Suyog Patil-54

Under the guidance of

Mr.Mrugendra Vasmatkar
 INDEX

sr. no.. Content page no.

1. Problem statement 2
2. Theory 2
3. Design and Diagram 4
4. VHDL programming 5
5. RTL schematics 8
6. Simulation Window 9
7. Conclusion and 10
Bibliography

PROBLEM STATEMENT:-
Design a 2-dimensional binary multiplier to multiply two four bit numbers
to get eight bit binary product using VHDL language

SOFTWARE REQUIREMENTS:- Xilinx ISE 14.7

THEORY:-

A binary multiplier is an electronic circuit used in digital electronics, such

as a computer, to multiply two binary numbers. It is built using binary
adders.

A variety of computer arithmetic techniques can be used to implement a

digital multiplier. Most techniques involve computing a set of partial
products, and then summing the partial products together. This process is
similar to the method taught to primary schoolchildren for conducting
long multiplication on base-10 integers, but has been modified here for
application to a base-2 (binary) numeral system.

A binary computer does exactly the same which we learned in school

about multiplication, but with binary numbers. In binary encoding each
long number is multiplied by one digit (either 0 or 1), and that is much
easier than in decimal, as the product by 0 or 1 is just 0 or the same
number. Therefore, the multiplication of two binary numbers comes down
to calculating partial products (which are 0 or the first number), shifting
them left, and then adding them together (a binary addition, of course).

For example:
 1011 (this is 11 in binary)
x 1110 (this is 14 in binary)
======
0000 (this is 1011 x 0)
+ 1011 (this is 1011 x 1, shifted one position to the left)
+ 1011 (this is 1011 x 1, shifted two positions to the left)
+ 1011 (this is 1011 x 1, shifted three positions to the left)
=========
10011010 (this is 154 in binary)

DESIGN AND DIAGRAM:-

● Here, we have used two 4-bit binary numbers as: x3 x2 x1 x0 and

y3 y2 y1 y0 whose multiplication gives the result as:
p7 p6 p5 p4 p3 p2 p1 p0.
 ● Multiplication of 2 bits is done buy an AND gate whose output will
be e.g. y0 and x0 = y0×x0.
● These multiplied bits then added with shifted bit which are the
products of the next bits.
● At last addition of all bits is done column wise using a full adder to
get the product
● Here the subsequent sun of the adder is given to the next adder in
the next row and carry is given to the subsequent adder in the same
row.

VHDL PROGRAMMING:-
● Programming of this multiplier is done on the xilinx ISE software
using structural architecture.
● For structural architecture we have used different components of
the multiplier such as full adder and AND gate.
● In the structural programming first the components are made and
then its mapped into the the main program.
● Following is the vhdl code of the main program, multiplier:-

VHDL CODE:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity two2multi is
port(X,Y : IN BIT_VECTOR(3 DOWNTO 0);
P : OUT BIT_VECTOR(7 DOWNTO 0)
);
end two2multi;
architecture Behavioral of two2multi is
SIGNAL C1,C2,C3: BIT_VECTOR(3 DOWNTO 0);
SIGNAL S1,S2,S3: BIT_VECTOR(3 DOWNTO 0);
SIGNAL XY0,XY1,XY2,XY3 : BIT_VECTOR(3 DOWNTO 0);
COMPONENT FULLADDER
PORT(X,Y,Cin : IN BIT;
Cout,SUM : OUT BIT);
END COMPONENT;
COMPONENT HALFADDER
PORT(X,Y : IN BIT;
Cout,SUM : OUT BIT);
END COMPONENT;

begin
XY0(0) <= X(0) AND Y(0);XY1(0) <= X(0) AND Y(1);
XY0(1) <= X(1) AND Y(0);XY1(1) <= X(1) AND Y(1);
XY0(2) <= X(2) AND Y(0);XY1(2) <= X(2) AND Y(1);
XY0(3) <= X(3) AND Y(0);XY1(3) <= X(3) AND Y(1);
XY2(0) <= X(0) AND Y(2);XY3(0) <= X(0) AND Y(3);
XY2(1) <= X(1) AND Y(2);XY3(1) <= X(1) AND Y(3);
XY2(2) <= X(2) AND Y(2);XY3(2) <= X(2) AND Y(3);
XY2(3) <= X(3) AND Y(2);XY3(3) <= X(3) AND Y(3);
FA1 : FULLADDER PORT MAP
(XY0(2),XY1(1),C1(0),C1(1),S1(1));
FA2 : FULLADDER PORT MAP
(XY0(3),XY1(2),C1(1),C1(2),S1(2));
 FA3 : FULLADDER PORT MAP
(S1(2),XY2(1),C2(0),C2(1),S2(1));
FA4 : FULLADDER PORT MAP
(S1(3),XY2(2),C2(1),C2(2),S2(2));
FA5 : FULLADDER PORT MAP
(C1(3),XY2(3),C2(2),C2(3),S2(3));
FA6 : FULLADDER PORT MAP
(S2(2),XY3(1),C3(0),C3(1),S3(1));
FA7 : FULLADDER PORT MAP
(S2(3),XY3(2),C3(1),C3(2),S3(2));
FA8 : FULLADDER PORT MAP
(C2(3),XY3(3),C3(2),C3(3),S3(3));
HA1 : HALFADDER PORT MAP
(XY0(1),XY1(0),C1(0),S1(0));
HA2 : HALFADDER PORT MAP (XY1(3),C1(2),C1(3),S1(3));
HA3 : HALFADDER PORT MAP (S1(1),XY2(0),C2(0),S2(0));
HA4 : HALFADDER PORT MAP (S2(1),XY3(0),C3(0),S3(0));
P(0) <= XY0(0); P(1) <= S1(0); P(2) <= S2(0);
P(3) <= S3(0); P(4) <= S3(1); P(5) <= S3(2);
P(6) <= S3(3); P(7) <= C3(3);
end Behavioral;

MULTIPLIER:
RTL schematics :
HALF ADDER:
FULL ADDER:

SIMULATION WINDOW:-
CONCLUSION:

4-bit binary array multiplier has 8 full adders and 4 half adders and 16
AND gates. We have implemented this multiplier in structural
architecture with 3 components- full adder , half adder and an AND
gate. This multiplier is the basic building block of ALU in computers.
Simplicity of this multiplier is because its implementation is same as that
of simple multiplication algorithm which we use in the case of integers.

BIBLIOGRAPHY
● https://en.wikipedia.org/wiki/Binary_multiplier
● https://sites.google.com/ves.ac.in/mrugendra-
vasmatkar/