Switches, Lights, and Multiplexers: UNIT4

1
UNIT4:
Switches, Lights, and
Multiplexers
APRI 11 - 2007
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY
INTEGRATED CIRCUIT DESIGN RESEARCH AND EDUCATION CENTER
(ICDREC)

DEPUTY DIRECTOR
2
PURPOSE
Learn how to connect simple input and
output devices to an FPGA chip.
Learn how to implement a circuit that uses
simple input and output devices.
Simple input devices = swiches SW17-0.
Simple output devices = LEDs and 7-
segment displays.
Design multiplexers and 7-segment
decoder.
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG
3
PART I
Use 18 toggle switches (SW17-0) as input
to a circuit, and 18 red leds (LEDR17-0)
can be used to display output values.
4
Solution
1. module part1(SW,LEDR);
2. input [17:0]SW; //toggle switches
3. output [17:0]LEDR; //red LEDs
4. assign LEDR=SW;
5. endmodule
5
SIMULATION & PROGRAMMER
Launch the Quartus-II software.
Follow all steps in the first tutorial
Quartus II introduction using Verilog
design to simulation and program to
chip.

6
PRACTICE
Implement this part by these steps:
Create a new Project Wizard
Add and code a Verilog text editor.
Pin assignments.
Start Compilation.
Power on for Kit DE2.
Start program and download into the Kit.
Toggle the switches and view results in Leds.

7
PART II
Design a 8 bits wide 2-to-1 Multiplexer
s M[7:0]
0
Y[7:0] 1
X[7:0]
8
MULTIPLEXER
The designed multiplexer or mux is a
circuit that has two 8-bit inputs, X and Y,
and produces a output M with a selection
s.
Operation
If s=0 then M=X.
If s=1 then M=Y.
9
SIMPLE 2-TO-1 MUX
Simple 2-to-1 Mux:

Verilog code:
assign m=(~s & x)|(s & y);

10
IMPLEMENT A MULTIPLEXER
To implement a mux 8
bits wide, we can use 8
simple mux.
To describle it in Verilog
HDL, we will use 8
assign.
11
PRACTICE
Create a new project for your circuit.
Add and code a Verilog file for multiplexer
to your project.
Use SW
17
on DE2 kit as the s selector.
Use SW
7-0
as the X input and SW
15-8
as the
Y input.
Use LEDG
7-0
as display M output.
Connect SW to LEDR to display input.
12
PRACTICE (cont.)
Include the pin assignment file to your
project. (similar the tutorial).
Start compile your project.
Download the compiled circuit into chip.
Test the functionality of your project by
toggle switches and view results in leds
display.
13
PART III
Design a 5-to-1 Multiplexer.
14
5-TO-1 MULTIPLEXER
A 5-to-1 multiplexer is similar 2-to-1
multiplexer with 5 inputs instead of 2
inputs and three inputs as selector.
Output will be one of 5 inputs.
15
OPERATION
A 5-to-1 mux use 5 inputs: U, V, W, X and
Y and a output m has to be selected one
of 5 input with 3-bit selectors s
2
s
1
s
0
.

A 5-to-1 mux can be build by using 2-to-1
mux which was design in previous part.
16
OPERATION (cont)
17
IMPLEMENT 5-TO-1 MUX
The 5-to-1 multiplexer has principle similar
the 2-to-1 multiplexer, so the
implementation will be similar.
A 3-bit wide 5-to-1 multiplexer will use 3
one bit wide 5-to-1 multiplexer.
Note: in dont care state the output will
select y input.
18
PRACTICE
19
PRACTICE (cont)
assign m_i[1] = (~S[0] & U[i]) |
(S[0] & V[i])
m_i[1]
assign m_i[2] = (~S[0] & W[i]) |
(S[0] & X[i])
m_i[2] m_i[3]
assign m_i[3] = (~S[1] & m_i[1])
| (S[1] & m_i[2])
assign M[i] = (~S[2] & m_i[3]) |
(S[2] & Y[0])
20
PRACTICE (cont)
Add and code a Verilog file for multiplexer
to your project. Only use assign statement.
Use SW
17-15
on DE2 kit as the s
2
s
1
s
0

selector.
Use SW
14-0
as five 3-bit inputs U to Y.
Use LEDG
2-0
as display M output.
21
PRACTICE (cont)
display.
Ensure that all input can be selected.
22
PART3 CASE STATEMENT
[2:0]S is a wire net
[2:0] U,V,W,X,Y are a
wire net
[2:0]M is a register
variable.
always @(S or U or V or W or X
or Y)
case (S)
.
. (code not show)
.
endcase
23
PART IV
Design a seven-segment decoder.
Display H, E, L, O and blank characters on
7-segment display.
24
7-SEGMENT DECODER
A 7-segment decoder has
3 inputs c
2
c
1
c
0
and 7
outputs that use to display
a character on a 7-
segment display.
The 7-segment display in
DE2 kit is active low level.
True table
25
C2 C1 C0 Char H0 H1 H2 H3 H4 H5 H6
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
H
E
L
O
Blank
Blank
Blank
Blank
1 0 0 1 0 0 0
0 1 1 0 0 0 0
1 1 1 0 0 0 1
0 0 0 0 0 0 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
2 1 0
C C C
2 1 0
C C C

2 1 0 2 1 0
2 1 0 2 1 0
0 H C C C C C C
C C C C C C

TRUE TABLE OF 7segment -DECODER
26
LOGIC FUNCTION
0 1 2 0 1 2
0 1 2 0 1 2 0 1 2 0 1 2
0 1 2 0 1 2 0 1 2 0 1 2
0 1 2 0 1 2 0 1 2
0 1 2 0 1 2
0 1 2 0 1 2
0 1 2 0 1 2
6
5
4
3
2
1
0
C C C C C C H
C C C C C C C C C C C C H
C C C C C C C C C C C C H
C C C C C C C C C H
C C C C C C H
C C C C C C H
C C C C C C H

27
IMPLEMENT A DECODER
Each segment is active by low level.
Use true table and/or Karnaugh map
(is it necessary?) to identify the
function of each segment in 7-
segment decoder.
Use only simple Verilog assign
statements to code your logic
function.
28
PRACTICE
Add and code a Verilog file for
decoder to your project.
Use SW
2-0
on DE2 kit as the c
2
c
1
c
0

input
Use HEX0 with 7 segment to display
output of the decoder.
29
PRACTICE (cont)
project.
toggle switches and view results on leds
and 7-segment display.
Ensure that H, E, L, O and blank can be
display.
30
PART4 CASE STATEMENT
[2:0]c is a wire
[0:6]led is a register variable
31
PART V
Design a mux and
7-segment
decoder that
can be display
HELLO word on
five 7-segment
(HEX4,HEX3,HEX2
,HEX1,HEX0)
display and it can
be able to rotate
this word in a
circular fashion.
32
DESIGN GUIDE
In this design, we
will use 5-to-1
multiplexer which
was design in part
III and 7-segment
decoder which
was design in part
IV.
The 7-segment
decoder will be
used to display
any character H,
E, L, O and blank
33
DESIGN GUIDE (cont)
We should use the circuits from Parts III
and IV as subcircuits.
We use five character to display a word,
so we need to use ve instances of each
of the subcircuits.
34
35
36
1. module part5 (SW, HEX0,HEX1,HEX2,HEX3,HEX4);
2. input [17:0] SW; // toggle switches
3. output [0:6] HEX0,HEX1,HEX2,HEX3,HEX4;// 7-seg displays
4. wire [2:0] M;
5. part3case M4 (SW[17:15], SW[14:12], SW[11:9], SW[8:6],
SW[5:3], SW[2:0], M);
6. part3case M3 (.)
(code not show)
part4case L4 (M, HEX0);
part4case L3 (M,HEX1);
1. (code not show)
.
1. endmodule
2. module part3case
3. .(code not show)
4. endmodule
5. module part4case
6. (code not show)
7. endmodule
CODE TEMPLATE
37
CODE TEMPLATE (cont)
1. // implements a 3-bit wide 5-to-1
multiplexer
2. module part3case (S, U, V W, X, Y M);
3. input [2:0] S, U, V W, X, Y;
4. output [2:0] M;
5. ...code not shown
6. endmodule
38
1. // implements a 7-segment decoder for H, E,
L, O, and blank
2. module part4case (c, led);
3. input [2:0] C; // input code
4. output [0:6] Display; // output 7-seg code
5. ...code not shown
6. endmodule
39
PRACTICE (cont)
Launch the Quartus-II software.
Add and code a Verilog file to your
project.
To practise easier, use the code template.

40
PRACTICE (cont)
Use SW
17-15
on DE2 kit to select each of
five instances of the 3-bit wide 5-to-1
multiplexer.
Use each three switches in SW
14-0
to
produce the patterns of characters.
Connect the outputs of the ve
multiplexers to the 7-segment displays
HEX4, HEX3, HEX2, HEX1, and HEX0.
Show the code template for more detail.

41
PRACTICE (cont)
and 7 segment display.
Ensure that all input can be selected.
42
PART VI
This part is extend your design in previous
part.
All eight 7-segment displays will be used
to display a HELLO word which can be
rotated.
43
TRUE TABLE OF PROJECT
44
DESIGN GUIDE
Design a decoder to display a HELLO word.
Design a 3-bit wide 8-to-1 multiplexer. It
can be implemented by use 7 2to1
multiplexer.

45
8-TO-1 MULTIPLEXER
In4
Out
0
In0
0
In2
S2
0 0
2to1
Mux
1
2to1
Mux
In1
1
1
In7
1
In3
2to1
Mux
In6
1
In5
0
0
S0
2to1
Mux
0
2to1
Mux
2to1
Mux
S1
1
2to1
Mux
1
46
CODE TEMPLATE
1. SW 17 16 15 Displayed characters
2. 0 0 0 ---HELLO
3. 0 0 1 --HELLO
4. 0 1 0 -HELLO-
5. 0 1 1 HELLO--
6. 1 0 0 ELLO---H
7. 1 0 1 LLO---HE
8. 1 1 0 LO---HEL
9. 1 1 1 O---HELL
47
1. module part5 (SW, HEX0);
2. input [17:0] SW; // toggle switches
3. output [0:6] HEX0; // 7-seg displays
4. wire [2:0] M;
5. mux 3bit_8to1 M0 (blank, blank,blank,
-- H, E, L, L, O, M);
6. char_7seg H0 (M, HEX0);
7. endmodule
48
PRACTICE (cont)
Add new project and code verilog to it.
Include pin assigment file.
Start compiler and then download it to
DE2 kit.
Check functions of project by toggle
switches and observing the 7-segment
displays.
49
SUMMARY
In this lab:
The 7-segment display decoder was
design and display the HELLO word
The 2-to-1, 5-to-1, 8-to-1 multipexers
were designed and rotated to your word
which displayed on 7-segment display.


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