Lesson 5

UNIT 5:
Numbers and Displays

APRI 13 - 2007
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY
INTEGRATED CIRCUIT DESIGN RESEARCH AND EDUCATION CENTER
(ICDREC)

DEPUTY DIRECTOR
PURPOSE
This is an exercise in designing
combinational circuits that can
perform:

Binary-coded-decimal (BCD) addition

Binary-to-decimal number conversion
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG
Part 1: Display the decimal
values on the 7-segment
displays
Content
We wish to display on the 7-segment displays
HEX3 to HEX0 the values set by the switches SW
15-0 .
Let the values denoted by SW15-12 , SW11-8,
SW7-4 and SW3-0 be displayed on HEX3, HEX2,
HEX1 and HEX0, respectively.
Your circuit should be able to display the digits
from 0 to 9, and should treat the valuations
1010 to 1111 as dont-cares.
Steps
Create a new project which will be used to
implement the desired circuit on the Altera DE2
board.
Write a Verilog le that provides the necessary
functionality. Include this le in your project and
assign the pins on the FPGA
Compile the project and download the compiled
circuit into the FPGA chip
Test the functionality of your design by toggling
the switches and observing the displays.
Instruction
B H
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 0 0 1 1 0
0 1 0 0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0 1 0 0
0 1 1 0 1 1 0 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1
1 1 1 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 0
1 0 1 0 x x x x x x x

Mimimize Boolean function
3 2 1 0 2 0
[0] HEXi B B B B B B
3 2 1 0
B B B B
2 0
B B
Using Karnaugh map to minimal
expression of a Boolean function
HEXi[0] = (B[2] & ~B[0]) | (~B[3] & ~B[2] & ~B[1] &
B[0])
HEXi[1] = (B[2] & ~B[1] & B[0]) | (B[2] & B[1] & ~B[0])
HEXi[2] = (~B[2] & B[1] & ~B[0])
HEXi[3] = (~B[2] & ~B[1] & B[0]) | (B[2] & ~B[1] &
~B[0]) |
(B[2] & B[1] & B[0])
HEXi[4] = (~B[1] & B[0]) | (~B[3] & B[0]) | (~B[3] & B[2]
& ~B[1])
HEXi[5] = (B[1] & B[0]) | (~B[2] & B[1]) | (~B[3] & ~B[2]
& B[0])
HEXi[6] = (B[2] & B[1] & B[0]) | (~B[3] & ~B[2] & ~B[1])
Part1 Case Statement
module bcdto7seg(B,H);
input [3:0]B;
output [6:0]H;
reg [6:0];
always @(B)
case (B)
(code not show)
endcase
endmodule
Part 2: Convert binary to
decimal
Converts a four-bit binary number V = v3 v2 v1
v0 into its two-digit decimal equivalent D =d1d0
The intent of this exercise is to use simple
Verilog assign statements to specify the required
logic functions using Boolean expressions. Your
Verilog code should not include any if-else, case,
or similar statements.
Content
Instruction
Minimization for Boolean function
of circuit A
z = 1 iff V > 9
z =
3 2 3 1
VV VV
Minimization for Boolean function
of circuit B (1 of 2)
Minimization for Boolean function of
circuit B (2 of 2)
Boolean function for circuit C
z = 0, HEX1 [0:6]= 7b1111111
z = 1, HEX1 [0:6] = 7b1001111
So, we have:
HEX1 [0:6] = 7b1 1111
z z
Verilog code:
assign HEX1[6:0] = {4b1111,~z,~z,1b1}
Steps
Make a Quartus II project.
Compile the circuit and use functional simulation
to verify the correct operation of your comparator,
multiplexers, and circuit A.
Augment your Verilog code to include circuit A in
Figure 1 as well as the 7-segment decoder.
Change the inputs and outputs of your code to use
switches SW 3-0 on the DE2 board to represent
the binary number V , and the displays HEX1 and
HEX0 to show the values of decimal digits d1 and
d0 .
Recompile the project, and then download the
circuit into the FPGA chip.
Test your circuit by trying all possible values of V
and observing the output displays.
PART2 BEHAVIORAL
ABSTRACTIONS
N = 7b1111111
n = 7b1111111 if
binarynum <= 9
= 7b1001111 if
binarynum >9
n = binarynum if binarynum <=9
= binarynum 10 if binarynum > 9
Part 3 : Ripple-Carry Adder
Content
Design a Ripple-Carry adder using
Full adder modules
A circuit for a full adder, which has
the inputs a, b, and ci , and produces
the outputs s and co .
S:sum bit , co:carry bit
Steps
Create a new Quartus II project.
Write a Verilog module for the full adder
subcircuit and write a top-level Verilog module
that instantiates four instances of this full adder.
Use switches SW7-4 and SW3-0 to represent the
inputs A and B , respectively. Use SW 8 for the
carry-in cin of the adder. Connect the SW
switches to their corresponding red lights LEDR,
and connect the outputs of the adder, cout and S
, to the green lights LEDG.
Include the necessary pin assignments for the
DE2 board, compile the circuit, and download it
into the FPGA chip.
Test your circuit by trying different values for
numbers A, B , and c in
Instruction
PART3 BEHAVIORAL
ABSTRACTIONS
We use arithmetic operator +
In Verilog, a reg type is interpreted as an
unsigned number
In Verilog, a integer type is interpreted as a
signed number in 2s complement form with
the rightmost bit as the least significant bit.
The net type (wire, wor,wand) is interpreted
as unsigned numbers
Thus, to synthesize an unsigned arithmetic
operator, the net or reg type is used.
Part 4: Adds 2 BCD digits
Content
Using conversion of binary numbers into decimal
digits to design a circuit that adds two BCD digits.

The inputs to the circuit are BCD numbers A and B ,
plus a carry-in, cin . The output should be a two-digit
BCD sum S1 S0 .

Note that the largest sum that needs to be handled
by this circuit is S1 S0 = 9 + 9 + 1 = 19.
Write your Verilog code using simple assign
statements to specify the required logic functions-do
not use other types of Verilog statements such as if-
else or case statements for this part of the exercise.
Steps
Create a new Quartus II project for your
BCD adder
You should use the four-bit adder circuit
from part III to produce a four-bit sum
and carry-out for the operation A + B .
A circuit that converts this 5-bit binary
into 2 BCD digits S1S0 can be designed in
a very similar way as the binary-to-
decimal converter from part II.

Use switches SW7-4 and SW3-0 for the inputs A
and B, respectively, and use SW 8 for the carry-in.
Display the BCD values of A and B on the 7-seg
displays HEX6 and HEX4, and display S1 S0 on
HEX1 and HEX0.
Since your circuit handles only BCD digits, check
for the cases when the input A or B is greater than
9. If this occurs, indicate an error by turning on
the green light LEDG 8 .
Download circuit into the FPGA chip and test it

Instruction
Boolean function of circuit A
Y = X3X2 + X3X1
Y = 1 iff X[3:0] > 9
Verilog code for circuit A:
assign LEDG[8] = ((A[3] & A[2]) | (A[3] &
A[1]) ) | ((B[3] & B[2]) | (B[3] & B[1]) )
Boolean function of circuit B
If C = 0 , S0_M = S0
If C = 1

S0_M[0] = S0[0]
S0_M[1] = ~S0[1]
S0_M[2] =
~S0[1]
S0_M[3] =
S0[1]
Implementation of circuit B
Implementation of circuit C
HEX1 = 7b1111111 iff Cout = 0
and S1 = 0
HEX1 = 7b1001111 iff Cout = 1 or
S1 = 1
Verilog code :
assign HEX1 = {1b1,
~(S1|Cout),~(S1|Cout), 4b1111};
Part 5 : Add two 2-digit BCD
numbers to three-digit BCD
Content
Design a circuit that can add two 2-digit
BCD numbers, A1 A0 and B1 B0 to
produce the three-digit BCD sum
S2S1S0.
Use two instances of your circuit from
part IV to build this two-digit BCD adder.
Steps
Use switches SW15-8 and SW7-0 to
represent 2-digit BCD numbers A1A0 and
B1B0, respectively.
The value of A1 A0 should be displayed on
the 7-segment displays HEX7 and HEX6,
while B1 B0 should be on HEX5 and HEX4.
Display the BCD sum, S2S1S0, on the 7-
segment displays HEX2, HEX1 and HEX0.
Download the circuit into the FPGA chip,
and test its operation.
Instruction
Part 6: Add two 2-digit BCD numbers
to three-digit BCD using if-else
statements
Content
Design a circuit that can add two 2-digit
BCD numbers, A 1 A0 and B1 B0 to
produce the three-digit BCD sum
S2S1S0.
But it different part 5 by using if-else
statements along with the Verilog > and +
operators.
Pseudo-code
1. T0 = A0 + B0
2. if (T0 >9) then
3. Z0 = 10;
4. c1 = 1;
5. else
6. Z0 = 0;
7. c0 = 0;
8. endif
9. S0 = T0 Z0
10. T1 = A1 + B1 + c1
11. if (T1 > 9) then
12. Z1 = 10;
13. c2 = 1;
14. else
15. Z1 = 0;
16. c2 = 0;
17. endif
18. S1 = T1 Z1
19. S2 = c2
Part 7 : Converts a 6-bit binary
number into a 2-digit decimal
number
Content
Design a combinational circuit that
converts a 6-bit binary number into a 2-
digit decimal number represented in the
BCD form.
Use switches SW5-0 to input the binary
number and 7-segment displays HEX1 and
HEX0 to display the decimal number.
Steps
Create a new Quartus II project for your
Verilog code.
Use the Quartus II RTL Viewer tool to
examine the circuit produced by compiling
your Verilog code.
Download your circuit onto the DE2 board
Instruction
1. if (bin6 < 10)
2. bcd_h = 4'h0;
3. bcd_l = bin6[3:0];
4. Endif

5. if (bin6 < 20)
6. bcd_h = 4'h1;
7. bcd_l = /* bin6 - 10 */ bin6[3:0] + 4'h6; // -10 =
11110110. So, add 6
8. Endif

9. if (bin6 < 30)
10. bcd_h = 4'h2;
11. bcd_l = /* bin6 - 20 */ bin6[3:0] + 4'hC; // -20
= 11101100. So, add 12
12. Endif

13. if (bin6 < 40)
14. bcd_h = 4'h3;
15. bcd_l = /* bin6 - 30 */ bin6[3:0] + 4'h2; // -30 =
11100010. So, add 2
16. endif

17. if (bin6 < 50)
18. bcd_h = 4'h4;
19. bcd_l = /* bin6 - 40 */ bin6[3:0] + 4'h8; // -40 =
11011000. So, add 8
20. Endif

21. if (bin6 < 60)
22. bcd_h = 4'h5;
23. bcd_l = /* bin6 - 50 */ bin6[3:0] + 4'hE; // -50 =
11001110. So, add 14
24. Endif

25. else
26. bcd_h = 4'h6;
27. bcd_l = /* bin6 - 60 */ bin6[3:0] + 4'h4;
// -60 = 11000100. So, add 4
28. end

Homeworks
Exercise 1
Design a circuit that can Multiply two 1-digit BCD
numbers, A and B to produce the 2-digit BCD sum S1S0.
Write your Verilog code using simple assign statements
to specify the required logic functions-do not use other
types of Verilog statements such as if-else or case
statements for this part of the exercise . Perform the
steps below:
1.Use switches SW7-4 and SW3-0 to represent 1-digit
BCD numbers A and B, respectively. The value of A
should be displayed on the 7-segment displays HEX6,
while B should be on HEX3. Display the BCD sum, S1S0,
on the 7-segment displays HEX1 and HEX0.
2.Make the necessary pin assignments and compile the
circuit.
3.Download the circuit into the FPGA chip, and test its
operation
Exercise 2
Repeat the exercise 1 but you can use if-
else statements along with the Verilog >
and + operators.

Lesson 5

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UNIT 5:

Numbers and Displays

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