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VALLURUPALLI NAGESWARA RAO VIGNANA JYOTHI

INSTITUTE OF ENGINEERING AND TECHNOLOGY

An Autonomous Institute, NAAC Accredited with ‘A++’ Grade (CGPA: 3.73/4.0) NBA

Accredited for CE, EEE, ME, ECE, CSE, EIE, IT B.Tech. Programmes

Approved by AICTE, New Delhi, Affiliated to JNTU-H, Recognised as “College with Potential for
Excellence” by UGC

Vignana Jyothi Nagar, Pragathi Nagar, Nizampet (S.O), Hyderabad TS 500 090 India

VLSI Design
Course Based Project Report
On

"Area and Time Efficient Architecture for Square of 4-bit number"

Submitted by:
CH.N.V.SRINIJA 19071A04J6

D. RAMYA SAI 19071A04J7

G.SURYA HARSHINI 19071A04Q4

T.SAI PRIYAMVADA 19071A04Q5

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s.no CONTENTS PAGE NO

1 ABSTRACT 3

2 INTRODUCTION 4

3 THE ARCHITECTURE 5-8

4 IMPLEMENTATION ON XILINX 9-11

5 SIMULATION RESULT 12

6 SCHEMATIC VIEW 13

7 CONCLUSION 14
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ABSTRACT
The boom of high speed recent communication hardly requires the
efficient Mathematical operations. The favored performance outcomes
of any architecture are possible only by the effective Mathematical
operations.
Squaring plays an essential role in high speed applications like
animation, Digital signal processing, and image processing, etc.
Where the speed is a crucial performance characteristic.
The project is about a high speed squaring circuit for binary numbers.
High speed Vedic multiplier is used for design of the proposed
squaring circuit. The key to our success is that only one Vedic
multiplier is used instead of four multipliers reported in the literature.
In addition, one squaring circuit is used twice. Our proposed Squaring
Circuit seems to have better performance in terms of speed.
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Introduction
Multiplication and squaring are most common and important
arithmetic operations having wide applications in different areas of
engineering and technology. The main motivation behind this work is
to investigate the VLSI Design and Implementation of Squaring
Circuit architecture with reduced delay.
Interestingly, only one multiplier is used here instead of four
multipliers reported in the literature. Here, one squaring circuit is used
twice to reduce delay we apply Vedic Sutras to binary multipliers
using carry save adders. In particular, we develop an efficient binary
multiplier architecture that performs partial product generations and
additions in parallel. With proper modification of the Vedic multiplier
algorithm, the squaring circuit is developed.
Here, the computation time involved is less. The combinational delay
and the device utilizations obtained after synthesis is compared. Our
proposed Vedic multiplier based Squaring Circuit seems to have better
performance in terms of speed. The hardware architecture of the
squaring circuit is presented.
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Architecture
We propose an efficient multiplier architecture using Vedic
mathematics. The ‘Urdhva Tiryagbhyam’ (Vertically and Crosswise)
sutra [2] has been traditionally used for the multiplication of two
numbers in the decimal number system. The motivation behind the
extension to binary number system is to make it compatible with the
digital hardware circuits. This Sutra is illustrated with the help of a
numerical example, where two decimal numbers are multiplied.
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We now extend the above idea (for multiplication) to binary number

system. Computer arithmetic [3,4] usually deals with binary number
systems. Thus, there is a strong need to develop efficient schemes for
multiplication of binary numbers. This may be noted that
multiplication of two bits A0 and B0 is nothing but an AND
operation.
Interestingly, this operation can easily be implemented using a two
input AND gate used in digital circuits. Further sake of simplicity,
each bit is represented by a Cross enclosed by a circle. Least
Significant Bit (LSB) R0 is obtained by multiplying the LSBs of the
multiplicand and the multiplier. Here, the multiplication process is
carried out according to steps displayed in Fig. 2. Further, digits on
both sides of the line are multiplied and added with the carry from the
previous step. All seven steps shown in Fig.2 are important. This
generates one of the bits of the result (Rn) and a carry (Cn). This carry
is added in the next step and, hence, the process goes on.
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A. 2x2 Vedic Multiplier Module For Binary Numbers:

Here, an efficient Vedic multiplier using carry save adder is presented.
The 2X2 Vedic multiplier module is implemented using two half-
adder modules and is displayed in Fig. 3. Very precisely we can state
that the total delay is only 2-half adder delays, after final bit products
are generated. It is wise to write Implementation Equations of 2X2
Vedic multiplier module for simulation. The implementation
equations are written as:
R0 (1-bit) = A0.B0 (8)
R1 (1-bit) = A1.B0 + A0.B1 (9)
R2 (2-bits) = A1.B1 + R1 (1) (10) Product =
R2 & R1 & R0 (11)
where ‘&’ denotes concatenation operation. Note that final result
(product) is obtained using Eq.(11).
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B. 2-Bit Squaring Circuit:

The 2X2 Vedic multiplier architecture is modified as shown in Fig. 5
to realise the 2-bit squaring circuit. Here, one half adder and one AND
gate are utilized instead of two half-adders as shown in Fig. 3.

C. 4-Bit Squaring Circuit:

A 4-bit squaring circuit is implemented using two 2-bit squaring
circuits (as shown in Fig.5) and one 2X2 Vedic Multiplier (as
displayed in Fig.3) instead of four 2X2 Vedic Multiplier modules. In
the same manner, 8-bit squaring circuit and 16-bit squaring circuits
are implemented using Vedic multiplier module and squaring circuits
of 4bit and 8-bit, respectively. Likewise, n-bit squaring circuit can be
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implemented taking one (n/2)-bit Vedic multiplier module and two

(n/2)-bit squaring circuits.

IMPLEMENTATION
SOFTWARE USED : Xilinx

SIMULATOR USED : ISim

PROCEDURE :

a) In the Xilinx project folder create a device with required configuration.

b) Add a new Verilog module file to the project.

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c) Write the Verilog code for required operation of circuit.

d) In Isim simulator run the behavioral check syntax and simulate behavioral model.

e) After simulation of the model, go to implementation part and under synthesize

view,the RTL schematic.

PROGRAM
main code

module project1(a,p);
input [3:0]a; output
wire [7:0]p; wire
[1:0]b; wire [1:0]c;
wire [3:0]b1; wire
[3:0]c1; wire [3:0]c2;
wire [3:0]c3; wire
[3:0]d; wire [5:0]c4;
wire ca,ca1,ca2; wire
[4:0]sum; assign
b[1:0]=a[3:2]; assign
c[1:0]=a[1:0];
square2bit f1 (b1,b);
multi2bit f2 (c1,b,c);
square2bit f3 (c2,c);
assign c3[3]=0; assign
c3[2]=0; assign
c3[1:0]=c2[3:2]; assign
d=0000;
carry_save f4 (c4,ca,c1,c1,c3,d,0); cla
f6 (b1,c4[5:2],0,ca2,sum1);
assign p[7:4]=sum1;
assign p[3:2]=c4[1:0];
assign p[1:0]=c2[1:0];
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endmodule

2 bit squaring circuit

module square2bit(out,a);
output [3:0]out; input
[1:0]a; assign out=a*a;
endmodule

2*2 multiplier

module multi2bit(out,a,b);
output [3:0]out; input
[1:0]a; input [1:0]b; assign
out=a*b;
endmodule

4 bit carry save adder

module fa(sum,carry,a,b,cin);
output sum,carry; input
a,b,cin; wire u,v,y; xor
g1(u,a,b); and g2(v,a,b); xor
g3(sum,cin,u); and
g4(y,cin,u);
or g5(carry,y,v); endmodule
module carry_save(sum,carry,a,b,cin,d,c);
output carry; output[4:0]sum;
input[3:0]a; input[3:0]b; input[3:0]cin;
input[3:0]d; input c;
wire cx0,cx1,cx2,cx3; wire
sx0,sx1,sx2,sx3; wire
cy0,cy1,cy2,cy3; wire
sy1,sy2,sy3,cz0,cz1,cz2; fa f1
(sx0,cx0,a[0],b[0],cin[0]); fa f2
(sx1,cx1,a[1],b[1],cin[1]);
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fa f3 (sx2,cx2,a[2],b[2],cin[2]);
fa f4 (sx3,cx3,a[3],b[3],cin[3]);
fa f5 (sum[0],cy0,d[0],sx0,c); fa
f6 (sy1,cy1,d[1],sx1,cx0); fa f7
(sy2,cy2,d[2],sx2,cx1); fa f8
(sy3,cy3,d[3],sx3,cx2); fa f9
(sum[1],cz0,cy0,sy1,c); fa f10
(sum[2],cz1,cy1,sy2,cz0); fa f11
(sum[3],cz2,cy2,sy3,cz1);
fa f12 (sum[4],carry,cy3,cx3,cz2);
endmodule

4 bit CLA adder

module cla(a,b,ci,co,s);
input [3:0]a,b; output
[4:0]s; input ci;
output co; wire
[3:0]G,P,C; assign G =
a&b; assign P = a^b;
assign co=G[3]+ (P[3]&G[2]) + (P[3]&P[2]&G[1]) + (P[3]&P[2]&P[1]&G[0]) +
(P[3]&P[2]&P[1]&P[0]&ci);
assign C[3]=G[2] + (P[2]&G[1]) + (P[2]&P[1]&G[0]) + (P[2]&P[1]&P[0]&ci);
assign C[2]=G[1] + (P[1]&G[0]) + (P[1]&P[0]&ci); assign C[1]=G[0] +
(P[0]&ci); assign C[0]=ci; assign s = {co,P^C}; endmodule
SIMULATION RESULT:

RTL SCHEMATIC:
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TECHNOLOGY SCHEMATIC:TECHNOLOGY SCHEMATIC:

 CONCLUSION
This project presents an unique method of Multiplication based on
Vedic Mathematics Using the vedic hierarchial overlay multiplier and
the novel vedic division algorithm lead to significant improvement in
performance.Vedic maths algorithms leads to faster mental
calculation.High speed VLSI arithmetic architectures can be derived
from vedic maths.Due to its parallel and regular structure the vedic
algorithms can be easily laid out on silicon chip.
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