4th International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB-18)
Design of an Efficient High Speed Radix-4 Booth
Multiplier for both Signed and Unsigned Numbers
D.Kalaiyarasi
Research Scholar
Department of Electrical and Electronics
Engineering
Sathyabama Institute of Science and Technology
Chennai, India
kalaiccarthi@yahoo.co.in
Abstract— This paper displays the design of an efficient High
speed Radix-4 Booth multiplier for both signed and unsigned
numbers. The Proposed Booth multiplier is the capable
multiplier which treats both positive and negative number
consistently dissimilar to conventional multiplier. Generally
multiplication can be performed by add and shift operation, in
which every multiplier bit creates one multiple bit of the
multiplicand that has to be added to the partial product. The
larger number of multiplicand has to be added when the
multiplier is larger in size; as a result the delay of the multiplier
is high. Since the delay depends upon the number of addition
operation. To obtain better performance, we need to minimize
the number of addition which in turn reduces the number of
partial product. The efficient algorithm that will minimize the
number of multiplicand is Booth algorithm. It has been proved
that it can be useful to apply the proposed Booth architecture in
high speed multipliers because of the gain in time obtained due to
reduction of partial products to k/2. The proposed multiplier
increases the speed by 62.411% than the Array multiplier with
almost same area (LUTs).
Keywords— Radix-4 Booth Multiplier, Array Multiplier, Partial
Product Generator, Signed and unsigned multiplication, Booth
Algorithm
I. INTRODUCTION
Multipliers plays very important role in many digital
systems such as calculators, microprocessor, digital filters,
and digital signal processor. They are also used in
implementation of discrete Fourier transform, Correlation,
Range measurement. The performance of any digital system is
usually measured in terms of the used multipliers, since the
process of the multiplication is very slow. Multiplication is
nothing but adds and shift algorithm which is considered as
series of repeated addition. That is the multiplicand adds itself
the multiplier number of times. To implementation this
multiplication, it requires a large number of hardware
elements and also it will operate at lower speed. To overcome
this problem many ideas have been proposed recently. With
978-1-5386-4606-9©2018 IEEE
M.Saraswathi
Associate Professor
Department of Electronics and Communication
Engineering
Panimalar Engineering College
Chennai, India
m.saraswathi16@yahoo.com
advance in technology, many researches were trying to design
multipliers with high speed, low area and low power
consumption or even integration of all in the single multiplier
which is suitable for real time application. Among this speed
is the most important parameter to be considered in many real
time applications. Generally, multiplication operation is
carried out by first generating the partial product and then
adding to it. The speed of the multiplier depends on how fast
the generation of partial product is done and they are added.
To speed up the generation of partial products, the number of
partial product has to be minimized and also the addition can
be speed up by using efficient adder.
The implementation of high speed data processing is
proposed for systolic array multiplier [1] and also introduced
the concept of parallel processing and pipelining that
improved the speed of execution. The number of partial
product array is minimized by one using radix-16 Booth
recoded magnitude multipliers is presented [2]. The design of
an efficient multiplier based on Modified Booth Algorithm is
carried out for both 4x4 and 8x8 bit numbers [3]. The
generation of partial product array with less number of partial
product terms is proposed with low area, complexity and
power consumption [4]. The Modulo multiplier is well
established with Low power and low area based RNS is
proposed [5]. The design and implementation of radix-16
booth Multiplier is proposed [6] and the number of partial
products were reduced to k/3 in radix-8 even further reduced
to k/4 by higher radix-16 multiplier. A high speed Booth
multiplier is designed with less number of flip-flops and
thereby the memory size is reduced [7]. The number of partial
products is determined by recoding type. The minimum
redundant digit set is obtained by recoding binary operand
into a signed-digit operand [8], [9]. The number of partial
products can be further minimized by using higher radix.
Although less popular than radix-4, there exist industrial
instances of radix-8 [10] – [14] and radix-16 multipliers [15]
in microprocessors implementations.
 4th International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB-18)

Array Multiplier is well known architecture which is based

on repeated addition and shifting. The area of array multiplier
is increased since it requires more number of logic gates. The
delay for the multiplier is also increased since the signal takes
long time to propagate through the gates. The Booth algorithm
is one of the most popular and efficient algorithm used to
minimize the number of partial products as a result the time
delay can be minimized. To compute multiplication, the
number system should be represented in 2’s complement form
which can be handled very easily by Booth algorithm. In this
paper we proposed an efficient architecture of Booth
multiplier for signed multiplication. The performances of the
proposed multiplier have been compared with an array
multiplier in terms of area, speed and layout.
This paper described briefly as follows: Section II
array architecture of multiplier is discussed and the efficient
architecture of proposed radix – 4 Booth multiplier in section
III. Section IV gives the simulation result of existing and
proposed work. The performance comparison between array
and Booth multiplier is discussed in section V. Conclusion in
section VI.
Fig.1 8 x 8 –bit signed array multiplier
II. ARRAY MULTIPLIER
Array Multiplier is well known architecture which is based
on repeated addition and shifting. The multiplication of the
multiplicand with one digit multiplier generates the partial
product which is shifted based on their bit sequence and then
added. An array multiplier accepts the multiplier and
multiplicand simultaneously to calculate the bit product xj * yk.
For ‘n’ bit multiplier it requires n-1 adders.
To determine the properties need for the array,
structure for multiplication sequence procedure is shown in
figure.1.
Each partial product term requires to calculate the bit
product xj * yk and then add it to other contribution in column
i=(j+k). This gives a sum
= ∗ + … … … … … … . (1)

For each product bit, an equivalent description of the

operation is obtained by writing the base-10 values

= ∗ 2 = ∗ 2 … (2)

And then forming the product, P =x*y

= ∗2 ∗2 … … … … … . (3)
Fig. 2 Architecture of Array Algorithm

The carry output bits are fed to next adder available in the
= ∗ ∗ 2 … … … … (4) column to the left like as carry save chain. It accepts
multiplier and multiplicand bit simultaneously and the longest
The term ∗ provides the bit value and 2 the delay during the calculation of product depends on the speed
weighting. of the adder. The carry chain in P15 that originate from the
The architecture of the proposed 8x8 signed Array carry bits P1 column and propagates through the P2-P14
multiplier is shown in Figure 2. This calculates the bit product quantities would be an obvious problem. In general, ‘n’ bit
∗ using AND gates and the product bits are formed using Array multiplier requires n*(n-2) full adders, ‘n’ half adders
half adders/ Full adders in each column. and n2 AND gates.

978-1-5386-4606-9©2018 IEEE
 4th International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB-18)

III. RADIX-4 BOOTH MULTIPLIER as k/2- digit for radix-4 algorithm, a k/3-digit for radix-8
The Proposed Booth multiplier is the capable multiplier algorithm, and so on. The major limitation of radix – 2
which treats both positive and negative number consistently algorithm is that it requires ‘k’ shifts with an average of k/2
dissimilar to conventional multiplier. Generally multiplication additions. It is overcome by radix-4 Booth algorithm which
can be performed by add and shift operation, in which every reduces the number of partial product to be added into ‘k/2’.
multiplier bit creates one multiple bit of the multiplicand that Table II shows the radix-4 multiplication in dot notation.
has to be added to the partial product. The larger number of TABLE II
multiplicand has to be added when the multiplier is larger in RADIX-4 MULTIPLICATION IN DOT NOTATION
size; as a result the delay of the multiplier is high. Since the
delay depends upon the number of addition operation. To
obtain better performance, we need to minimize the number of
Multiplicand x = ●●●●
addition which in turn reduces the number of partial product.
The efficient algorithm that will minimize the number of
multiplicand is Booth algorithm. Multiplier y= (●●)(●●)
The proposed Booth algorithm, examines the multiplier
word ‘y’ and searches for 0’s since these have no effect on the
Partial product bits ●●●● (y1y0)2 x40
sum. This may be used to encode groups of bits in ‘y’ to
produce a control digit that specifies the operation to be
● ●●● (y3y2)2 x41
performed on the multiplicand ‘x’.
Product P= ● ●●●●●●●
= 2 + 2 … … … … … … … (5)
At first, a “0” is placed to the right LSB of the
This may be written as multiplier. After that Three bits of the multiplicand is recoded
/ based on the Table III or using equation (8).
= ( + 2 )2 … … … … (6)
Example 1:
/
Multiplier = 0 1 0 1 1 10
= 2 … … … … … … … … … … … … . . (7)
First 0 is placed to the right LSB, we get
0 1 0 1 1 10 0
Where = 0 and
= + 2 … … … … … … … … … (8)
is the encoding digit since yk has a value of ‘0’ or ‘1’. The At a time three bits are selected with overlapping of MSB as
yk can have decimal values of +2,+1,0,-1,-2. To compute the follows:
product x*y using radix-4 Booth multiplier, we divide ‘y’ into
three bit segments that overlap by one bit. The last zero on the
right has been added for y-1 = 0. Each group gives a value of
yk that determines an operation. The product is computed by
providing a dual-word size register that holds the sum after
every operation is completed. The Table I summarizes the
meaning of the encoded values.
TABLE I SUMMARY OF BOOTH ENCODED DIGIT OPERATION
TABLE III RADIX-4 BOOTH RECODING
Effect on sum
0 0 0 0 Add ‘0’ yi+1 y yi-1 Ei/2
0 0 1 +1 Add ‘x’ 0 0 0 0
0 1 0 +1 Add ‘x’ 0 0 1 1
0 1 1 +2 Shift ‘x’ left, add
1 0 0 -2 Take 2’s (x), shift left, add 0 1 0 1
1 0 1 -1 Add 2’s(x) 0 1 1 2
1 1 0 -1 Add 2’s(x) 1 0 0 -2
1 1 1 0 Add 0
1 0 1 -1
1 1 0 -1
For a given range of numbers, a higher radix will lead to 1 1 1 0
fewer digits that are the k-bit binary number can be decimated

978-1-5386-4606-9©2018 IEEE
 4th International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB-18)

The Procedure for implementing the Booth Algorithm are

as follows

Step 1: Formation of Booth recoding table

Consider the multiplier in block of three, such that each

block overlaps the previous block by one bit and form the
table using Table I.

Step 2: Booth Algorithm

Fig.4 RTL view of 8x8 Array multiplier
The multiplicand may be added to the partial product,
subtracted from the partial product, or left unchanged
according to the Booth rule and then shifted.

Example 2:

Fig. 5 Device utilization summary of 8x8 Array multiplier

IV. SIMULATION RESULTS

The design of 8 x 8 –bit Array Multiplier and Radix-4

Booth multiplier have been simulated using Xilinx 14.1
platform and implemented on Spartan xc7a100t-3csg324. The
simulation results, RTL view, Device utilization summary,
Timing constraints, I/o planning-package, Floor planning -
Device and Floor planning - schematic diagram of array
multiplier is shown in Fig3,4,5,6,7,8 and 9 respectively.

Fig.6 Timing constraints of 8x8 Array multiplier

Fig .3 Simulation results of 8x8 Array multiplier Fig.7 I/O planning – Package of 8x8 Array multiplier

978-1-5386-4606-9©2018 IEEE
 4th International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB-18)

Fig.12 Device utilization summary of 8x8 Radix-4 Booth multiplier

Fig.8 Floor planning – Device of 8x8 Array multiplier

Fig.8 Floor planning – schematic of 8x8 Array multiplier

The simulation results, RTL view, Device utilization

summary, Timing constraints, I/o planning-package, Floor Fig.13Timing constraints of 8x8 Radix-4 Booth multiplier
planning -Device and Floor planning - schematic diagram of
Radix-4 Booth multiplier is shown in Fig10,11,12,13,14,15
and 16 respectively.

Fig.14 I/O planning – Package of 8x8 Radix-4 Booth multiplier

Fig.10 Simulation results of 8x8 Radix-4 Booth multiplier

Fig.15 Floor planning – Device of 8x8 Radix-4 Booth multiplier

Fig.11 RTL view of 8x8 Radix-4 Booth multiplier

978-1-5386-4606-9©2018 IEEE
 4th International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB-18)
Adder”, International Journal of Engineering and Management
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V. CONCLUSION
The design of 8 -bit Array Multiplier and Radix-4 Booth
multiplier have been simulated using Xilinx 14.1 platform and
implemented on Spartan xc7a100t3csg324. The proposed
radix-4 Booth multiplier increases the speed by 62.411% than
the Array multiplier with almost same area (LUTs).It has been
proved that it can be useful to apply a radix-4 Booth
architecture in high speed multipliers because of the gain in
time obtained due to reduction of partial products to k /2.
Delay has been further reduced by replacing CSA with
koggestone parallel prefix adder in the summation stage in
future.
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