Department of Biomedical Engineering

CSE-221L – Digital Logic Design

Semester: 4th (Spring 2023)

Lab Instructor: Engr. M. Hamza Zulfiqar Session: Fall, 2021

Date: /2023

LAB-7 4-Bit Ripple Carry Adder

Name Reg. No. Marks

2021 – BME –
35
7.1 Objectives

The objectives of this experiment are

• To analyze the performance of 4-bit ripple carry adder and draw its truth table
• To implement 4-bit ripple carry adder using basic gates only
• To implement 4-bit ripple carry adder using universal gates only
7.2 Theory

Full adder’s implementations in last lab shown that single 1-bit binary adders can be constructed from
basic logic gates. But what if its required to add together two n-bit numbers, then n number of 1-bit
full adders need to be connected or “cascaded” together to produce what is known as a Ripple Carry
Adder.

7.2.1 4 Bit Ripple Carry Adder

A “ripple carry adder” is simply “n“, 1-bit full adders cascaded together with each full adder
representing a single weighted column in a long binary addition. It is called a ripple carry adder
because the carry signals produce a “ripple” effect through the binary adder from right to left, (LSB to
MSB).

For example, suppose we want to “add” together two 4-bit numbers, the two outputs of the first full
adder will provide the first place digit sum (S) of the addition plus a carry-out bit that acts as the carry-
in digit of the next binary adder.

The second binary adder in the chain also produces a summed output (the 2nd bit) plus another carry-
out bit and we can keep adding more full adders to the combination to add larger numbers, linking
the carry bit output from the first full binary adder to the next full adder, and so forth. The block
diagram of a 4-bit ripple carry adder with 4-bit inputs A, and B and C input and 4-bit S, 1 bit COUT as
outputs is shown in Figure 7.1.

Figure 7.1 Block diagram of 4-bit Ripple carry adder.

One main disadvantage of “cascading” together 1-bit binary adders to add large binary numbers is
that if inputs A and B change, the sum at its output will not be valid until any carry-input has “rippled”
through every full adder in the chain because the MSB (most significant bit) of the sum has to wait for
any changes from the carry input of the LSB (less significant bit). Consequently, there will be a finite
delay before the output of the adder responds to any change in its inputs resulting in an accumulated
delay. Circuit diagram of carry propagation and to obtain the 4-bit sum is shown in Figure 7.2.

Figure 7.2 Implementation of 4-bit ripple carry adder using AND, OR and XOR.

When the size of the bits being added is not too large for example, 4 or 8 bits, or the summing speed
of the adder is not important, this delay may not be important. However, when the size of the bits is
larger for example 32 or 64 bits used in multi-bit adders, or summation is required at a very high clock
speed, this delay may become prohibitively large with the addition processes not being completed
correctly within one clock cycle.

This unwanted delay time is called Propagation delay. Also another problem called “overflow” occurs
when an n-bit adder adds two parallel numbers together whose sum is greater than or equal to 2n.

One solution is to generate the carry-input signals directly from the A and B inputs rather than using
the ripple arrangement above. This then produces another type of binary adder circuit called a Carry
Look Ahead Binary Adder where the speed of the parallel adder can be greatly improved using carry-
look ahead logic.
The advantage of carry look ahead adders is that the length of time a carry look ahead adder needs in
order to produce the correct SUM is independent of the number of data bits used in the operation,
unlike the cycle time a parallel ripple adder needs to complete the SUM which is a function of the total
number of bits in the addend.

Assume you want to add two operands A and B with C in = 0 where

A= A3 A2 A1 A0

B=B3 B2 B1 B0

For example:

A= 1 0 1 1 +

B= 1 1 0 1

---------------

A+B= 11 0 0 0 = C out S3 S2 S1 S0

4-bit full adder circuits with carry look ahead features are available as standard IC packages in the
form of the TTL 4-bit binary adder 74LS83 or the 74LS283 and the CMOS 4008 which can add together
two 4-bit binary numbers and generate a SUM and a CARRY output as shown in Figure 7.3.

Figure 7.3 4-bit full adder IC.

7.3 Equipment

• DC Power Source / Power Supply

• Prototype Development Board
• Connecting Wires

7.4 Components

• ICs (7400, 7404, 7408, 7432, 7483, 7486)

• 330 Ω / 1 kΩ resistor ¼ watt Measured: ________________________
• LEDs

7.5 Procedure

1. Place the development board gently on the observation table.

2. Fix the IC which is under observation between the half shadow line of breadboard, so there is no
shortage of voltage.
3. Connect the wire to the main voltage source (Vcc) whose other end is connected to last pin of the
IC (14 place from the notch).
4. Connect the ground of IC (7th place from the notch) to the ground terminal of supply/kit.
5. Give the input at any one of the gate of the ICs i.e. 1st, 2nd, 3rd, 4th gate by using connecting
wires. (In accordance to IC provided).
6. Connect the interconnected inputs and outputs of different ICs.
7. Connect output pins to the led on the breadboard through current limiting resistor.
8. Switch on the power supply.
9. If led glows then output is true, if it didn’t glows then output is false, which is numerically denoted
as 1 and 0 respectively.

7.6 Precautions

1. All connections should be made neat and tight.

2. Digital lab supplies, components and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Never touch live and naked wires.

7.7 Obersvations

Table 7.1 Observation Table of 4-bit Ripple Carry Adder.

Input A Input B CIN Sum Carry COUT

A3 A2 A1 A0 B3 B2 B1 B0 C0 S3 S2 S1 S0 C3 C2 C1 C4
7.8 Results

Table 7.2 Truth Table of 4-bit Ripple Carry Adder

Input A Input B CIN Sum COUT

A3 A2 A1 A0 B3 B2 B1 B0 CIN S3 S2 S1 S0 COUT

7.9 Analysis

1. What is half adder?

2. Write the Boolean expression for the sum and carry of full adder.
3. How many full adders are required to construct an m-bit adder?

4. Draw the block diagram of 2-bit adder as a combination of half adders.

7.10 Conclusion

7.11 Home Assignment

Perform the experiment using Proteus/LogiSim and submit the screenshots of software
implementation in the form of brief technical report (7.12 Lab Report).

Report must include the simulation based implementation of 4-bit ripple carry adder using lowest
number of gates, basic gates and universal gates. Report also includes the pictures of hardware based
implementation of ripple carry adder from lab for different input combinations.
 Assessment Rubrics
CSE-221L – Digital Logic Design – Lab 07
Name: _______________________ Reg. No.: ____2021-BME-____________
Method: Lab reports, viva, and instructor observation during lab sessions.
Outcome Assessed:
a. Ability to conduct experiments and projects, analyze and interpret the acquired data, and synthesize information to
derive valid conclusions for digital logic circuits. (P2) (PLO – 04)
b. Ability to students will be able to implement digital logic circuits simulations through modern tools. (P2) (PLO – 05).
c. Ability to contribute effectively and ethically as a team member towards the completion of labs and semester project.
(A2) (PLO – 09).
d. Ability to report and explain their project, experimental results, and findings effectively in written as well as in oral
communication. (C2) (PLO – 10).

Performance Meets expectation (4-5)
Focused attention on the experiment.
Does proper calibration of equipment,
1. Conducting
carefully examines equipment and
Experiment
build circuits through relevant
[1]
components, and ensures smooth
operation and process.
Plans data collection to achieve
2. Data
experimental objective/s, and
Collection
conducts an orderly and a complete
[1]
data collection.
Accurately conducts simple
computations and statistical analysis
using collected data; correlates
experimental results to known
3. Data
theoretical values; accounts for
Analysis [1]
measurement errors and parameters
that affect experimental results.
Able to interpret the lab all-important
results and data comparisons
4. Realization
correctly; good understanding of labs
[1]
is conveyed.
Use computer to implement the
5. Modern
circuits through simulations and
Tool Usage
collect data effectively.
[2]
Actively engages in lab and
cooperates with other group members.
6. Teamwork
Also complete the labs and
[3]
submissions in an effective manner
and adhering to ethical values.
The report illustrates an accurate and
thorough understanding of scientific
concepts underlying the lab and
includes the experimental results and
7. Lab Report
findings flawlessly or with some
[4]
mistakes. All figures, graphs, tables
are correctly drawn, are numbered
and contain titles/captions or with few
formatting mistakes.
Lacking in expectation (3-2)
Focus was lost on several
occasions. Calibrates equipment,
examines equipment and build
circuits through relevant
components, and operates the
equipment with minor error.
Plans data collection to achieve
experimental objective/s and
collects complete data with minor
error.
Conducts simple computations
and statistical analysis using
collected data with minor error;
reasonably correlates
experimental results to known
theoretical values; attempts to
account for measurement errors
and parameters that affect
experimental results.
Able to interpret the lab some of
results and data comparisons
correctly; fair understanding of
labs is conveyed.
Uses computer to implement
the DLD circuits through
simulations and collect data
with minor errors.
Cooperates with other group
members in a reasonable manner
for the conduct of the lab and
complete the labs in an effective
manner as well as ethically.
The report illustrates a limited
understanding of scientific
concepts underlying the lab and
includes the experimental
results and findings with major
deficiencies. Most figures,
graphs, tables OK, some still
missing some important or
required features.
Does not meet expectation (1-0) Marks
Students were hostile about
participating or unable to do so. Or
unable to calibrate appropriate
equipment and build circuits through
relevant components, and equipment
operation is substantially wrong.
Does not know how to plan data
collection to achieve experimental
goal/s; data collected is incomplete
and contain errors.
Unable to conduct simple statistical
analysis on collected data; no
attempt to correlate experimental
results with known theoretical
values; incapable of explaining
measurement errors or parameters
that affect the experimental results.
Unable to interpret the lab results
and comparison of data, a lack of
understanding of results. Or
incorrect interpretation of data is
conveyed.
Does not know how to use
computer for the implementation
of DLD circuits through
simulations and collect data.
Distracts or discourages other group
members from conducting the
experiment and effective and ethical
submission.
The report illustrates inaccurate
understanding of scientific concepts
underlying the lab or did not submit
the lab report on time or/and having
major deficiencies. Figures, graphs,
tables contain errors or are poorly
constructed, have missing titles,
captions or numbers, units missing
or incorrect, etc.

Total

Lab Instructor:
Name: __Engr. M. Hamza Zulfiqar_ Signature: _______________________

Date: __________________________