ADVANCE VLSI DESIGN

PRACTICAL FILE

VARUN SAHANI
04216412811
M.Tech (ECE) 2nd sem

INDEX

S.No

EXPERIMENT

DATE

TEACHERS
SIGN

EXPERIMENT 1
AIM: Design the layout of PMOS.
THEORY: The PMOS transistor is the equivalent but uses an N substrate with P source and
drain. It conducts when no current is applied at the gate and shuts off when current is applied.
The symbols for PMOS transistors are shown in the figure.
P-type metal-oxide semiconductor logic uses p-type metal-oxide-semiconductor field effect
transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors
have four modes of operation: cut-off (or sub threshold), triode, saturation (sometimes called
active), and velocity saturation. The p-type MOSFETs are arranged in a so-called "pull-up
network" (PUN) between the logic gate output and positive supply voltage, while a resistor is
placed between the logic gate output and the negative supply voltage. The circuit is designed
such that if the desired output is high, then the PUN will be active, creating a current path
between the positive supply and the output.
LOGIC SYMBOL

Fig. 1.1 PMOS Transistor

STICK DIAGRAM & LAYOUT OF P-MOS TRANSISTOR

Fig 1.2 (a) Stick Diagram of PMOS Transistor

Fig 1.2 (a) Layout of PMOS Transistor

EXPERIMENT 2
AIM: Design the layout of NMOS.
THEORY: The image shows an NMOS transistor. When current is applied to its input the gate is
pushed into the P substrate and connects the two N areas (source and drain). Thus current flows
from the source to the drain. The symbols for NMOS transistors are shown in the figure. N-type
metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field effect transistors
(MOSFETs) to implement logic gates and other digital circuits. NMOS transistors have four
modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and
velocity saturation.
The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic
gate output and negative supply voltage, while a resistor is placed between the logic gate output
and the positive supply voltage. The circuit is designed such that if the desired output is low,
then the PDN will be active, creating a current path between the negative supply and the output.
LOGIC SYMBOL

Fig. 2.1 PMOS Transistor

STICK DIAGRAM & LAYOUT OF NMOS TRANSISTOR

Fig 2.2 (a) Stick Diagram of NMOS Transistor

Fig 2.3 (a) Layout of NMOS Transistor

EXPERIMENT 3
AIM: Design the layout of CMOS INVERTER.

THEORY: CMOS inverters (Complementary MOSFET Inverters) are some of the most widely
used and adaptable MOSFET inverters used in chip design. They operate with very little power
loss and at relatively high speed. Furthermore, the CMOS inverter has good logic buffer
characteristics, in that, its noise margins in both low and high states are large.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the
NMOS source terminal, were VIN is connected to the gate terminals and Vo is connected to the
drain terminals.(See diagram). It is important to notice that the CMOS does not contain any
resistors, which makes it more power efficient that a regular resistor-MOSFET inverter. As the
voltage at the input of the CMOS device varies between 0 and 5 volts, the state of the NMOS and
PMOS varies accordingly.
LOGIC SYMBOL & TRUTH TABLE

(a)

(b)

Fig. 3.1 (a) NOT Gate and (b) Truth table of NOT Gate
CIRCUIT DIAGRAM

Fig. 3.2 Circuit Diagram of NOT Gate

STICK DIAGRAM & LAYOUT OF CMOS INVERTER

Fig. 3.3 (a) Stick Diagram of CMOS Inverter

Fig. 3.3 (b) Layout of CMOS Inverter

EXPERIMENT 4
AIM: Design the layout of 2 I/P NAND gate.
THEORY: The NAND gate is a digital logic gate that behaves in a manner that corresponds to
the truth table. A LOW output results only if all the inputs to the gate are HIGH. If one or more
inputs are LOW, a HIGH output results. The NAND gate is a universal gate in the sense that any
Boolean function can be implemented by NAND gates.
NAND gates can also be made with more than TWO inputs, yielding an output of LOW if all the
inputs are HIGH, and output of HIGH if any of the input is LOW.

The circuit below has two inputs and one output.

Whenever at least one of the inputs is low, the corresponding P-type transistor is
conducting while the N-type transistor will be closed.
Consequently, the output voltage will be HIGH
Conversely, if both inputs are HIGH, then each P-type transistor at the top will be open
circuits and both N-type transistors will be conducting. Hence the output voltage is low.
The function of this gate is summarized in the following truth table.

LOGIC SYMBOL & TRUTH TABLE

(a)
(b)
Fig. 4.1 (a) 2 Input NAND Gate and (b) Truth table of 2 Input NAND Gate
CIRCUIT DIAGRAM

Fig. 4.2 Circuit Diagram of 2 Input NAND Gate

STICK DIAGRAM & LAYOUT OF 2 I/P NAND GATE

Fig. 4.3 (a) Stick Diagram of 2 Input NAND Gate

Fig. 4.3 (a) Layout of 2 Input NAND Gate

EXPERIMENT 5
AIM: Design the layout of 2 I/P NOR gate.
THEORY: The NOR Gate is a digital logic gate that implements logical NOR-it behaves according
to the truth table. A HIGH output (1) results if all the inputs to the gate are low (0).if one or all
input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator.
NOR is a functionally complete operation combination of NOR gates can be combined to generate
any other logical function. By contrast, the OR operator is monotonic as it can only change LOW to
HIGH but not vice versa.

The circuit below has two inputs and one output.

Whenever at least one of the inputs is high, the corresponding N- type transistor will be
closed, while the P-type transistor will be open
Consequently, the output voltage will be low
Conversely if all inputs are low then all P-type transistors at the top will be closed circuits and
N- type transistors will be open.
Hence, the output voltage is high.
The function of this gate can be summarized by the following table:
LOGIC SYMBOL & TRUTH TABLE

(a)
(b)
Fig. 5.1 (a) 2 Input NOR Gate and (b) Truth table of 2 Input NOR Gate
CIRCUIT DIAGRAM

Fig. 5.2 Circuit Diagram of 2 Input NOR Gate

STICK DIAGRAM &LAYOUT OF 2 I/P NOR GATE

Fig. 5.3 (a) Stick Diagram of 2 Input NOR Gate

Fig. 5.3 (b) Layout of 2 Input NOR Gate