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ROLL: BT14ECE056
EXP 3
AIM: Find the delays in CMOS inverter circuit.
Schematic diagram:-
SPICE NETLIST:
* C:\Users\CHAITU\Documents\tphl tplh.asc
M1 N001 N002 Vout N001 PMOS
M2 Vout N002 0 0 NMOS
V1 N001 0 1.8
V2 N002 0 PULSE(0 1.8 1u 0.5u 0.5u 4u 8u)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Program Files (x86)\LTC\LTspiceIV\lib\cmp\standard.mos
.tran 0 20u 0
.meas TRAN Trise TRIG V(Vout)=10% of Vout RISE=1 TARG V(Vout)=90% of Vout
RISE=1
.meas TRAN Tfall TRIG V(Vout)=10% 0f Vout FALL=1 TARG V(Vout)=90% of Vout
FALL=1
.meas TRAN Tphl TRIG V(Vout)=0.9 FALL=1 TRAG V(V2)=0.9 RISE=1
.meas TRAN Tplh TRIG V(Vout)=0.9 RISE=1 TRAG V(V2)=0.9 FALL=1
.meas TRAN Tpd PARM {(Tphl+Tplh)/2}
.backanno
.end
RESULT:
trise=-1.12577e-007 FROM 1.36277e-006 TO 1.25019e-006
tfall=-1.12577e-007 FROM 1.36277e-006 TO 1.25019e-006
tphl=1.87498e-005 FROM 1.25019e-006 TO 2e-005
tplh=1.42497e-005 FROM 5.75026e-006 TO 2e-005
tpd=2e-005 FROM 0 TO 2e-005