PATEL TIMIR(U18EC038)

EXPERIMENT – 2
Date: 03/08/2021

AIM:
a) Implement the pull-up and pull-down network circuits. Assume Initial Conditions
suitably and perform Transient Analysis.

b) Implement a standard CMOS inverter. Plot VTC and note down output critical voltages.
Then implement the same circuit with interchanged transistors and repeat.

DESIGN SPECIFICATIONS:
VDD = 5V ,

(W/L)n = 1 ,

(W/L)p = 2.5 ,

Vtp = -0.8v ,

Vtn = 0.8V Technology

= 1u

THEORY:
Pull-up & Pull-down Networks:

Pull-up is a network that provides a low resistance path to Vdd when output is logic '1' and
provides a high resistance to Vdd otherwise. Pulldown is a network that provides a low
resistance path to Gnd when output is logic '0' and provides a high resistance to Gnd otherwise.
Pull up means getting close VDD. So PMOS has VDD as source, naturally when input is zero
drain would be pulled up. When output at zero PMOS turns on, it will be pulled high. Pull down
means bring output to Zero from One too. If input is One for an inverter in CMOS, N transistor
will be drive the output to Zero as pull down.

If we use PMOS in pull down network, then its gate terminal should be provided with a negative
voltage. Similarly, if we use NMOS in pull up network, then its gate terminal should be
provided with a voltage that is more positive than Vdd. So the voltages corresponding to logic
states at input are different from that at output. Hence two such 'CMOS' gates cannot be
interfaced directly. In other words, for PMOS as PDN and NMOS as PUN, VOH<VIH and
VOL>VIL which will result in negative noise margin. And hence this logic family would be
incompatible with itself.
 PATEL TIMIR(U18EC038)

CMOS Inverter (Interchanged NMOS and PMOS):

When pmos and nmos are interchanged in CMOS inverter it gives a buffer with weak output
states. If again the PMOS transistor be from Vcc down so when its input goes low it passes and
pulls the output high opposite to the NMOS one be at ground so when input goes high then
output goes low.

For input 1, the output would be a degraded 1 (as pull-up NMOS is not strong conductor of
Logic 1).

For input 0, output would be a degraded 0 (as the pull-down PMOS is not strong conductor of
Logic 0).

CIRCUIT DIAGRAM:
a) Pull-up and Pull-down

b) CMOS Inverter (Interchanged NMOS and PMOS):

 PATEL TIMIR(U18EC038)

CODE: a_1) PMOS as

PULL-UP:

*PMOS PUP

.model pmos PMOS VTO=-0.8 mos1

out in 1 1 pmos W=2.5u L=1u c1

out 0 1p IC=0V

Vdd 1 0 5

Vin in 0 pulse (0 5 2N 2N 2N 50N 100N)

.tran 0.1N 200N UIC

.control run
plot V(in) V(out)

.endc

.end

SIMULATION RESULT:

a_2) NMOS as PULL-UP:

 PATEL TIMIR(U18EC038)

*NMOS PUP .model nmos NMOS

VTO=0.8 mos1 1 in out out nmos

W=2.5u L=1u c1 out 0 1p IC=0V

Vdd 1 0 5

Vin in 0 pulse (0 5 2N 2N 2N 50N 100N)

.tran 0.1N 200N UIC

.control run
plot V(in) V(out)

.endc
.end

SIMULATION RESULT:

a_3) PMOS as PULL-DOWN:

*PMOS PDN
 PATEL TIMIR(U18EC038)

.model pmos PMOS VTO=-0.8 mos1 0

in out out pmos W=2.5u L=1u c1 out

0 1p IC=5V

Vin in 0 pulse (0 5 2N 2N 2N 50N 100N)

.tran 0.1N 200N UIC

.control run

plot V(in) V(out)

.endc

.end

SIMULATION RESULT:

a_4) NMOS as PULL-DOWN:

*NMOS PDN
 PATEL TIMIR(U18EC038)

.model nmos NMOS VTO=0.8

mos1 out in 0 0 nmos W=2.5u L=1u

c1 out 0 1p IC=5V

Vin in 0 pulse (0 5 2N 2N 2N 50N 100N)

.tran 0.1N 200N UIC

.control run

plot V(in) V(out)

.endc
.end

SIMULATION RESULT:

b_1) CMOS Inverter:

*CMOS inverter
 PATEL TIMIR(U18EC038)

.model nmos NMOS VTO=0.8

.model pmos PMOS VTO=-0.8

mos1 out in 1 1 pmos W=2.5u L=1u mos2

out in 0 0 nmos W=1u L=1u

Vdd 1 0 5

Vin in 0 5

.dc vin 0 5 0.01

.control run

plot V(out) V(in)

.endc
.end

SIMULATION RESULT:

b_2) CMOS Inverter (Inverted PMOS and NMOS):

*CMOS Interchanged inverter

.model nmos NMOS VTO=0.8

 PATEL TIMIR(U18EC038)

.model pmos PMOS VTO=-0.8

mos1 1 in out out nmos W=2.5u L=1u

mos2 0 in out out pmos W=1u L=1u

Vdd 1 0 5

Vin in 0 5

.dc vin 0 5 0.01

.control run

plot V(out) V(in)

.endc

.end

SIMULATION RESULT:

OBSERVATION TABLE:

NETWORK VOH (V) VOL (V)

PMOS PUN 5 0
 PATEL TIMIR(U18EC038)

NMOS PUN 4.15 0

PMOS PDN 5 0.85

NMOS PDN 5 0

CIRCUIT VOH (V) VOL (V) VIH (V) VIL (V) VTH (V)

CMOS Inverter 5 0 3.2 2.6 2.88

CMOS
Interchanged 4.2 0.8 3.31 1.7 2.5
Inverter

CONCLUSION:
a) By this experiment we have learned both the pull up network and the pull down network
circuits for PMOS and NMOS and by doing the transient analysis, computed the output
parameters. On comparing the parameters for PMOS as PDN and NMOS as PUN that
results in negative noise margin.

b) In this experiment we have implemented the Standard CMOS inverter and then
interchanged the PMOS and NMOS and computed the output, input parameters along
with the threshold voltage for the given specifications for both the cases, we found out
that on interchanging the transistors it gives a buffer with weak output states as
explained in the theory section.