PATEL TIMIR(U18EC038)

EXPERIMENT-6
AIM:
Consider pseudo-NMOS inverter with an NMOS size of 0.5mm/0.25mm. Study the effect of
sizing the PMOS device on the impact on following parameters.
➢ VOL
➢ Power dissipation
➢ tphl and tplh
➢ Noise margins NMH and NML

The W/L ratio of the grounded PMOS is to be varied for values of 4, 2, 1, 0.5 and 0.25. The devices
less than W/L < 1 is constructed by making the length longer than the width. Use 0.25 mm technology,
VDD = 2.5 V
Design the pseudo NMOS inverter to satisfy constraints:
1.Power dissipation < 41 mW
2.tphl< 14 ps

Theory:
The circuit consists of an NMOS pull-down network that realizes the logic function. The
entire PUN is replaced with a single load device that pulls up the output when the PDN is
turned off. The sizing of the load device relative to the pull-down devices is used to trade-off
parameters such a noise margin, propagation delay and power dissipation
The clear advantage of this gate over Standard CMOS is the reduced number of transistors.
N+1 transistors to implement an N-input gate.
 PATEL TIMIR(U18EC038)

1.Pseudo NMOS DC analysis

Code:
*Pseudo NMOS inverter VTC
.model nmos NMOS VT0=0.7 kp=60u
.model pmos PMOS VT0=-0.7 kp=20u

M1 out4 0 1 1 pmos W=1u L=0.25u

M2 out4 in 0 0 nmos W=0.5u L=0.25u

M3 out2 0 1 1 pmos W=0.5u L=0.25u

M4 out2 in 0 0 nmos W=0.5u L=0.25u

M5 out1 0 1 1 pmos W=0.25u L=0.25u

M6 out1 in 0 0 nmos W=0.5u L=0.25u

M7 out0.5 0 1 1 pmos W=0.5u L=1u

M8 out0.5 in 0 0 nmos W=0.5u L=0.25u

M9 out0.25 0 1 1 pmos W=0.25u L=1u

M10 out0.25 in 0 0 nmos W=0.5u L=0.25u

vdd 1 0 2.5
vin in 0 2.5
.dc vin 0 2.5 0.01 .control run plot v(in) v(out4)
v(out2) v(out1) v(out0.5) v(out0.25)
.endc
.end
 PATEL TIMIR(U18EC038)

Simulation Plot:

2.Pseudo NMOS Transient analysis

Code:
*Pseudo NMOS inverter transient

.model nmos NMOS VT0=0.7 kp=60u

.model pmos PMOS VT0=-0.7 kp=20u

M1 out4 0 1 1 pmos W=1u L=0.25u

M2 out4 in 0 0 nmos W=0.5u L=0.25u

M3 out2 0 1 1 pmos W=0.5u L=0.25u

M4 out2 in 0 0 nmos W=0.5u L=0.25u

M5 out1 0 1 1 pmos W=0.25u L=0.25u

M6 out1 in 0 0 nmos W=0.5u L=0.25u

M7 out0.5 0 1 1 pmos W=0.5u L=1u

 PATEL TIMIR(U18EC038)

M8 out0.5 in 0 0 nmos W=0.5u L=0.25u

M9 out0.25 0 1 1 pmos W=0.25u L=1u

M10 out0.25 in 0 0 nmos W=0.5u L=0.25u

vdd 1 0 2.5
vin in 0 pulse (0 2.5 0.8u 0.8u 0.8u 100u
200u)

.tran 0.1u 800u UIC

.control run

plot v(in) v(out4) v(out2) v(out1) v(out0.5) v(out0.25)

.endc
.end

Simulation Plot:
 PATEL TIMIR(U18EC038)

3.Pseudo NMOS Power dissipation

i)for (W/L)p = 4
Code:
*Pseudo NMOS inverter Power Dissipation
.model nmos NMOS VT0=0.7 kp=60u
.model pmos PMOS VT0=-0.7 kp=20u
M1 out4 0 1 1 pmos W=1u L=0.25u
M2 out4 in 0 0 nmos W=0.5u L=0.25u
vdd 1 0 2.5
vin in 0 2.5
.dc vin 0 2.5
0.01 .control
run plot I(VDD)
.endc
.end

Simulation Plot:
 PATEL TIMIR(U18EC038)

ii)for (W/L)p = 2
Code:

*Pseudo NMOS inverter Power Dissipation

.model nmos NMOS VT0=0.7 kp=60u
.model pmos PMOS VT0=-0.7 kp=20u

M1 out4 0 1 1 pmos W=0.5u L=0.25u

M2 out4 in 0 0 nmos W=0.5u L=0.25u
vdd 1 0 2.5
vin in 0 2.5
.dc vin 0 2.5
0.01 .control
run

plot I(VDD)

.endc
.end

Simulation Plot:
 PATEL TIMIR(U18EC038)

(W/L)p = 1

*Pseudo NMOS inverter Power Dissipation

.model nmos NMOS VT0=0.7 kp=60u

.model pmos PMOS VT0=-0.7 kp=20u

M1 out4 0 1 1 pmos W=0.25u L=0.25u

M2 out4 in 0 0 nmos W=0.5u L=0.25u
vdd 1 0 2.5
vin in 0 2.5
.dc vin 0 2.5 0.01
.control

run plot
I(VDD)
.endc
.end

Simulation Plot:
 PATEL TIMIR(U18EC038)

(W/L)p = 0.5

*Pseudo NMOS inverter Power Dissipation

.model nmos NMOS VT0=0.7 kp=60u

.model pmos PMOS VT0=-0.7 kp=20u

M1 out4 0 1 1 pmos W=0.5u L=1u

M2 out4 in 0 0 nmos W=0.5u
L=0.25u
vdd 1 0 2.5
vin in 0 2.5
.dc vin 0 2.5 0.01
.control

run plot
I(VDD)
.endc
.end

Simulation Plot:
 PATEL TIMIR(U18EC038)

(W/L)p = 0.25

*Pseudo NMOS inverter Power Dissipation

.model nmos NMOS VT0=0.7 kp=60u
.model pmos PMOS VT0=-0.7 kp=20u
M1 out4 0 1 1 pmos W=0.25u L=1u
M2 out4 in 0 0 nmos W=0.5u L=0.25u
vdd 1 0 2.5
vin in 0 2.5
.dc vin 0 2.5
0.01 .control
run plot I(VDD)
.endc
.end

Simulation Plot:
 PATEL TIMIR(U18EC038)

Observation:
DC Analysis:
(W/L)p VOH VOL VIH VIL NMH NML

4 2.5V 0.76V 2.25V 1.5V 0.25V 0.74V

2 2.5V 0.33V 1.9V 1.3V 0.6V 0.97V
1 2.5V 0.157V 1.6V 1.1V 0.9V 0.943V
0.5 2.5V 0.08V 1.5V 1V 1V 0.92V
0.25 2.5V 0.04V 1.2V 0.9V 1.3V 0.86V

Transient Analysis:
(W/L)p TPHL TPLH τp

4 0.28μs 0.3μs 0.29μs

2 0.14μs 0.14μs 0.14μs

1 0.05μs 0.05μs 0.05μs

0.5 0.02μs 0.02μs 0.02μs

0.25 0.1μs 0.09μs 0.095μs

(W/L)p Imax Power(static)

4 130μA 325μW
2 64.8μA 162μW
1 32.4μA 81μW
0.5 16.2μA 40.5μW
0.25 8.10μA 20.25μW

CONCLUSION:
In this experiment we have designed and analysed pseudo NMOS and its functionality and
for different values of W/L ratio of the PMOS. We observed a change in the propagation
delay with change in the width to length ratio and found out to be proportional to each other.
Hence the pseudo NMOS inverter to satisfy constraints: (i)Power dissipation < 41 mW (II)tphl< 14
ps is (W/L)p=0.5,0.25.