PATEL TIMIR(U18EC038)

EXPERIMENT-5
AIM:
Design a symmetrical CMOS inverter circuit, using minimum size transistors, to obtain τp = 0.8μs.

Design Specifications:
CLOAD = 100pF,
VDD = 3.3V,
VT0,n = 0.7V , VT0,p = -0.7V
μnCox = 60 μA/V2μpCox = 20 μA/V2
1 μm Technology
Design the inverter and verify your design for meets 1 μm Technologyusing a suitable
WINSPICE code.

Procedure:
Assume (W/L)n = 1/1

Step 1:
Kn = μnCox (W/L)n = 60(1/1) = 60 μA/V2
VGS,n = Vin = VDD = 3.3V Vt,n = 0.7V VDS,n = VDD/2 = 1.65V
Iavg,HL = 0.5{(Kn/2)(VGS,n – Vt,n)2 + (Kn/2)(2(VGS,n – Vt,n)VDS,n – VDS,n2) }
Iavg,HL = 0.5{(60μ/2)(3.3– 0.7)2 + (60μ /2)(2(3.3 – 0.7)1.65 – 1.652) }
Iavg,HL = 189.2625μA

Step 2:
TPHL = 0.872 μsτp = 0.8 μs
τp = (TPHL + TPLH)/2
0.8μ = (0.872μ + TPLH)/2
TPLH = 0.728μs

Step 3:
CLoad = 100pF V50% = 1.65V VOL = 0V TPLH = 0.728 μs
TPLH = CLoad (V50% - VOL)/Iavg,LH
0.728 μ = 100p (1.65 - 0)/Iavg,LH
Iavg,LH = 226.6484 μA
 PATEL TIMIR(U18EC038)

Step 4:
VGS,p = Vin - VDD = -3.3V Vt,p = -0.7V VDS,p = (VDD/2) - VDD= -1.65V
Iavg,LH = 0.5{(Kp/2)(VGS,p – Vt,p)2 + (Kp/2)(2(VGS,p – Vt,p)VDS,p – VDS,p2) }
226.6484μ = 0.5{(Kp/2)(-3.3 + 0.7)2 + (Kp/2)(2(-3.3 + 0.7)(-1.65) – (-1.65)2) }

=>Kp = 71.8521μA/V2
Kp = μpCox (W/L)p
=>71.8521μ= 20μ (W/L)p
=> (W/L)p = 3.59 ≈ 3.6

Code:
*CMOS inverter with given specs of propagation delay

.modelnmos NMOS VTO=0.7 kp = 60u

.modelpmos PMOS VTO=-0.7 kp = 20u

M1 out in 1 1 pmos W=3.6u L=1u

M2 out in 0 0 nmos W=1u L=1u
C out 0 100p
vdd 1 0 3.3
vin in 0 0 pulse (0 3.3 0.8u 0.8u0.8u 100u 200u)
.tran 0.1u 800u UIC
.control
run
plot V(in) V(out)
.endc
.end
 PATEL TIMIR(U18EC038)

Simulation Plot:

Calculation:
TPLH = 0.885μs TPHL = 1.027μs
τp = (TPHL + TPLH)/2
τp = (1.027μ + 0.885μ)/2
τp = 0.956μs

Observation:

Parameters Theoretical Practical

TPLH 0.728μs 0.885μs

TPHL 0.872μs 1.027μs

τp 0.8μs 0.956μs

Conclusion:
In this experiment we have designed CMOS inverter for the given specifications to
obtain τp = 0.8μsand then implemented the CMOS in WINSPICE and compared both
theoretical and practical values of TPHL, TPLH and τp.
 PATEL TIMIR(U18EC038)

ASSIGNMENT
AIM:
Design a symmetrical CMOS inverter circuit, which satisfies given delay constraints.

TPHL ≤ 5.86 μs and TPLH≤ 4.14μs

Design Specifications:
CLOAD = 200pF,
VDD = 5V,
VT0,n = 0.8V , VT0,p = -0.8V
μnCox = 40 μA/V2μpCox = 20 μA/V2
1 μm Technology
Design the inverter and verify your design for meets 1 μm Technologyusing a suitable
WINSPICE code.

Procedure:
Step 1:
CLoad = 200pF V50% = 2.5V VOH = 5V TPHL ≤ 5.86 μs
TPHL = CLoad (VOh - V 50%)/Iavg,HL
5.86 μ = 200p (5 – 2.5)/Iavg,HL
Iavg,HL = 85.3242 μA

Step 2:
CLoad = 200pF V50% = 2.5V VOL = 0V TPLH ≤ 4.14μs
TPLH = CLoad (V50% - VOL)/Iavg,LH
4.14 μ = 200p (1.65 - 0)/Iavg,LH
Iavg,LH = 120.7729μA

Step 3:
VGS,n = Vin = VDD = 5V Vt,n = 0.8V VDS,n= VDD/2 = 2.5V
Iavg,HL = 0.5{(Kn/2)(VGS,n – Vt,n)2 + (Kn/2)(2(VGS,n – Vt,n)VDS,n – VDS,n2) }
85.3242μ = 0.5{(Kn/2)(5– 0.8)2 + (Kn /2)(2(5 – 0.8)2.5 – 2.52) }

Kn= 10.5371μA/V2
 PATEL TIMIR(U18EC038)

Kn = μnCox (W/L)n
=>10.5371μ = 40μ(W/L)n
=> (W/L)n = 0.2634/1 =1/3.8

Step 4:
VGS,p = Vin - VDD = -5V Vt,p = -0.8V VDS,p = (VDD/2) - VDD= -2.5V
Iavg,LH = 0.5{(Kp/2)(VGS,p – Vt,p)2 + (Kp/2)(2(VGS,p – Vt,p)VDS,p – VDS,p2) }
120.7729 μ = 0.5{(Kp/2)(-5 + 0.8)2 + (Kp/2)(2(-5 + 0.8)(-2.5) – (-2.5)2) }

=>Kp = 14.9148μA/V2
Kp = μpCox (W/L)p
=>14.9148μ= 20μ (W/L)p
=> (W/L)p = 0.7457/1≈ 0.75/1 = 3/4

Code:
*CMOS inverter with given specs of TPLH and TPHL

.modelnmos NMOS VTO=0.8 kp = 40u

.modelpmos PMOS VTO=-0.8 kp = 20u

M1 out in 1 1 pmos W=3u L=4u

M2 out in 0 0 nmos W=1u L=3.8u
C out 0 200p
vdd 1 0 5
vin in 0 0 pulse (0 5 0.8u 0.8u0.8u 100u 200u)
.tran 0.1u 800u UIC
.control
run
plot V(in) V(out)
.endc
.end
 PATEL TIMIR(U18EC038)

Simulation Plot:

Calculation:
TPLH = 4.11μs TPHL = 5.80μs
τp = (TPHL + TPLH)/2
τp = (5.80μ + 4.11μ)/2
τp = 4.955μs

Observation:

Parameters Theoretical Practical

TPLH ≤ 4.14μs 4.11μs

TPHL ≤ 5.86μs 5.80μs

τp ≤ 5μs 4.955μs

Conclusion:
In this experiment we have designed CMOS inverter for the given specifications to
obtain TPHL ≤ 5.86 μs and TPLH ≤ 4.14 μsand then implemented the CMOS in WINSPICE
and compared both theoretical and practical values of TPHL, TPLH and τp.