SPICE Modeling of the CD4007 CMOS Dual Complementary

Pair Plus Inverter, Packaged in a 14-Pin Dip

The CD4007 has three PMOS and three NMOS transistors one pair is
connected as an inverter, the other two pairs are connected at the
gates, all three PMOS are connected at the n-well which must be at
the highest circuit potential, all three NMOS are connected at the p-
well and must be at the lowest circuit potential.

The SPICE model for the transistors in the CD4007 can be obtained by
making measurements on the individual PMOS and NMOS FETs. The
SPICE model can be verified by comparing the Family of curves and
Id-Vgs DC sweep curves from SPICE with the measured curves.

The SPICE model for transient circuit analysis such as oscillator

operation, gate delay investigations or other circuit timing require
size information such AD, AS, PD, PS in addition to L and W and oxide
thicknesses for the gate oxide and field oxide. Furthermore this
package includes electrostatic protection devices on each pin which
adds resistors and junction capacitance connected to the gate, drain
and source. To obtain estimates of this size information the black
epoxy package was etched away and dimensions on the bare chip
was measured using a calibrated microscope.

The SPICE models below work great for DC analysis such as Voltage
Transfer Curves (VTC). For Transient analysis the results are less
accurate because of inaccurate knowledge of the ESD circuitry sizes
and values. Adding a series resistors and capacitor s to the circuit to
model the ESD circuitry is possible. The chip layout shows that the
PMOS transistors are wider than the NMOS transistors thus W, AD,
AS, PD, PS are larger for the PMOS transistor
*Dr. Lynn Fuller, Professor, Rochester Institute of Technology 1-12-15
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=2u W=160u Ad=750p As=550p Pd=330u Ps=220u nrd=0.1 nrs=0.1
.MODEL RIT4007N7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8
+VTH0=1.5 U0= 600 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=3.44E-4 MJ=0.5 PB=0.95
+CJSW=2.07E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=2.3E-10 CGDO=2.3E-10 CGBO=1.06E-10)
*
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=2u W=320u Ad=1500p As=1100p Pd=630u Ps=420u nrd=0.1 nrs=0.1
.MODEL RIT4007P7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8
+VTH0=-1.5 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=3.44E-4 MJ=0.5 PB=0.94
+CJSW=2.07E-10 MJSW=0.5 PBSW=0.94
+CGSO=2.3E-10 CGDO=2.3E-10 CGBO=1.06E-10)

20um
DRAIN
4um
SOURCE

GATE

L=2u Ad=750p Pd=330u

W=160u As=550p Ps=220u
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=2u W=160u Ad=750p As=550p Pd=330u Ps=220u nrd=0.1 nrs=0.1
.MODEL RIT4007N7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8
+VTH0=1.5 U0= 600 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=2u W=320u Ad=1500p As=1100p Pd=630u Ps=420u nrd=0.1 nrs=0.1
.MODEL RIT4007P7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8
+VTH0=-1.5 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)

20um

4um
DRAIN
SOURCE

GATE
L=2u Ad=750p Pd=330u
W=160u As=550p Ps=220u
PMOS SPICE family of curves up to -5 volts on gate and drain.
NMOS SPICE family of curves up to 5 volts on gate and drain.
Checking operation at maximum rated voltage of 20 volts
Ring Oscillator including 25pF to model internal ESD devices
* 23 April 2014 Anthony Aiello
* UTMOST is software that extracts SPICE model parameters from measured I-V curves
* Level 11 is BSIM3 in Silvaco UTMOSTIV; may have to change 11 to 49 for other
* simulators; AC and junction parameters taken from Dr. Fuller's CD4007
* models; LINT and WINT, XJ, NCH, TOX assumed a reasonable value

.MODEL cd4007n NMOS (

+LEVEL = 49 VERSION = 3.3 TNOM = 23
+TOX = 1e-07 XJ = 1e-06 NCH = 2e+16
+VTH0 = 1.14098 K1 = 2.12491 K2 = 0.2
+U0 = 0.0165798 UA = 1e-12 UB = 1.31485e-16
+UC = 3.45708e-09 VSAT = 189307 A0 =2
+AGS = 0.481611 B0 = 5.4717e-06 B1 =0
+KETA = 0.034434 A1 = 0.0462264 A2 = 0.926415
+RDSW = 100 WR =1 WINT = 1e-06
+LINT = 1e-07 VOFF = -0.0394991 NFACTOR = 0.320755
+CIT = 0 CDSC = 0.00024 CDSCD = 0
+CDSCB = 0 ETA0 = 0 ETAB = 0
+PCLM = 0.001 PDIBLC1 = 0 PDIBLC2 = 0.0086
+PDIBLCB = 0 DROUT = 0.56 PVAG = 1.03774
+DELTA = 0.0915943 IS = 2.15472e-13 MOBMOD = 1
+CAPMOD = 2 CGDO = 2.3e-10 CGSO = 2.3e-10
+CGBO = 1.065e-10 CJ = 0.000344 PB = 0.95
+MJ = 0.5 CJSW = 2.07e-10 PBSW = 0.95
+MJSW = 0.5 NOFF = 1 ACDE = 1
+MOIN = 15 )

.MODEL cd4007p PMOS (

+LEVEL = 49 VERSION = 3.3 TNOM = 23
+TOX = 1e-07 XJ = 1e-06 NCH = 2e+16
+VTH0 = -1.84155 K1 = 1.26511 K2 = -0.158237
+U0 = 0.0102413 UA = 1e-10 UB = 1.31598e-16
+UC = 7.77036e-10 VSAT = 136236 A0 = 1.1276
+AGS = 1.86085 B0 = 3.26359e-05 B1 = 1e-07
+KETA = -0.0886792 A1 =0 A2 = 0.933116
+RDSW = 100 WR =1 WINT = 1e-06
+LINT = 1e-07 VOFF = 0.0245283 NFACTOR = -0.00943396
+CIT = 0 CDSC = 0.00024 CDSCD = 0
+CDSCB = 0 ETA0 = 0.0190291 ETAB = -0.00754717
+PCLM = 1.98788 PDIBLC1 = 0.0414112 PDIBLC2 = 0.0086
+PDIBLCB = 0 DROUT = 0.56 PVAG = 0
+DELTA = 0.0937923 IS = 2e-13 MOBMOD = 1
+CAPMOD = 2 CGDO = 2.3e-10 CGSO = 2.3e-10
+CGBO = 1.06e-10 CJ = 0.000344 PB = 0.95
+MJ = 0.5 CJSW = 2.07e-10 PBSW = 0.95
+MJSW = 0.5 NOFF = 1 ACDE = 1
+MOIN = 15 )
This figure show the parasitic diodes in the CD4007 chip. Each diode
represents a capacitance that should be included when doing SPICE
transient analysis. The resistors along with the reverse biased diodes
provide electrostatic discharge protection (ESD).