Patel Timir(U18EC038)

EXPERIMENT – 6
Date: 13/09/2021
AIM: Draw the diagram and explain in detail with suitable mathematical
expression and waveforms for measurement of phase difference using SR latch
(NOR latch) method for the following condition:
The input is sinusoidal having 3 𝑉 peak-to-peak amplitude and frequency 2 𝑘𝐻𝑧,
the all pass filter capacitance value is 0.1 𝜇𝐹, select the value of variable
resistance to produce phase value of 45°, 60° other resistance assumed to be
equal.
THEORY:
A phase detector or phase comparator is a frequency mixer, analog multiplier or logic
circuit that generates a voltage signal which represents the difference in phase between two signal inputs.
It is an essential element of the phase-locked loop (PLL). Detecting phase difference is very important in
many applications, such as motor control, radar and telecommunication systems, servo mechanisms, and
demodulators. All pass filter is used in order to provide the phase difference. An RC filter is used in order
to provide spikes so as to avoid the S=1 and R=1 (invalid state) for the SR Latch.
 Patel Timir(U18EC038)
CIRCUIT DIAGRAM:

SIMULATION RESULT:
For 45° For 60°

OBSERVATION TABLE:
Phi(Th) Delta T R taken Phi(prac) Error(%)
45° 64.8μs 330 ohm 46.65° 3.6%
60° 85.42μs 460 ohm 61.5° 2.5%
 Patel Timir(U18EC038)
CALCULATION:

F= 2kHz & C=0.1µF 𝛥𝑡 = 85.42𝜇𝑠

Tan(𝝓/2)= 2πf *R *C 𝝓(Prac)= 360 *f *∆t

For 𝝓=60°

R= [tan(60/2)] / 2*3.14*0.1*10-6

⸫ R = 459.67Ω

𝝓(Prac) = 360*2*103*85.42*10-6

⸫ 𝝓(Prac) = 61.5°

Absolute Error = |(60°-61.5°)/60°|

= 0.025

Absolute PercentageError (%) = 0.025*100

= 2.5%

CONCLUSION:
In this experiment, we have successfully implemented a SR Latch with
the help of NOR gates. We calculated the phase difference with the help of SR Latch
based on the inputs from operational amplifiers and observed the output at various stage.