Q1)

Ic vs Vbe

Ic vs Vce

Ic vs Vbe
 Ic vs Vce

Q2)

I haven’t found any RED LED in the Ltspice, please consider the LED that I included as my calculations and all correct.
Here Vc is the LED across voltage, also I have included Vbe, Vce and Vled separately due to lack of trace in combined
diagram, I have included the combined plot also.

The waveforms approximately matched the expected values. Applying KVL in the Vcc to ground loop, 3.3- Ic * 23
– V_ec – V_diode=0. Since the V_diode= 2.65(from datasheet), theoretical values of Veb=0.7V, Vec=0.2. Therefore
from the above equation, Ic=19.6mA and Ib=Ic/beta= 19.6mA/200=98uA.

Fig: Switching circuit to drive a LED

Vbe vs time
Vce vs time

V_LED vs time

Vbe, Vce, V_LED vs time

 Ib and Ic vs time

The waveforms approximately matched the expected values.

Applying KVL in the Vcc to ground loop, 3.3- Ic * 23 – V_ec – V_diode=0

Since the V_diode= 2.65(from datasheet), theoretical values of Veb=0.7V, Vec=0.2. Therefore from the above
equation, Ic=19.6mA and Ib=Ic/beta= 19.6mA/214=91.58uA.

I was unable to find A1015 transistor, so please consider the transistor SST3906. Compared to the transistor ST3906,
2N3906 transistor has a switching delay of 0.01ns so the transistor SST3906 is fast in switching.

Fig: Switching circuit to drive a LED

Vbe vs time

Vce vs time

V_LED vs time
Vbe, Vce, V_LED vs time

Ib and Ic vs time
 Fig: pulse generator circuit with transistor 2N2222 -RC time constant is 10ms(expected pulse duration)

Waveforms are approximate as expected, the calculations are as follows.

For t<0:
Q1:OFF, Q2:ON, Q3:OFF.

Vc+=Vc1= 6V, Vc-=Vb2= 0.7V and Vout= 0.2V

For t=0+:
Q1:ON, Q2:OFF, Q3:ON.

Vc+=Vc1= 0.2V, Vc-=Vb2= -6+0.2= -5.8V and Vout= 6V

For t>>>0:
Q1:OFF, Q2:ON, Q3:OFF.

Vc+=Vc1=6V, Vc-=Vb2=0.7V and Vout=0.2V

Pulse generator with 2N3019

As compared to 2N3019 part transistor the part: 2N2222 giving good characteristics and slight high voltage also.
Fig: Self sustained pulse generator, initially we have to give a trigger (monostable multivibrator case), then
feedback from output to input will help in producing self-sustained pulse
Fig: Schmidt Trigger circuit to smooth out the input pulse
 Fig: Final circuit of the pulse generator after including the two schmidt trigger circuit

Q3a)
Fig: current source
Q3b) Here, in this circuit load to Q1 is a 20mA current mirror circuit that is having constant resistance, but
the load at Q3 is R4 which we are varying, the base voltage of the coupled transistors Q2 and Q3 is
constant, so to maintain a constant voltage at the base of the Q2 and Q3 (of course coupled) the current
will decrease according to the increase in load resistance RL.

Recordings from simulation.

RL Value Current through RL

100ohm 19.8mA
1kohm 8 mA
10kohm 0.8mA
100kohm 80uA

Q4)

the gates given in the question are an inverter, NAND and NOR gates.

Q) what considerations do we have to make for the gate's drain resistor values?

A) We should choose Rd such that the voltage drop across it is maintained to keep the MOSFET operating in between
saturation and cut-off region since the slope of the DC load line is -1/R_D.

R_D = (V_DD-V_DS)/I_D; where I_D is the current of the MOSFET operating in the saturation region. I_D can be
obtained from the formula I_D=1/2u C_ox W/L (V_GS – V_T)^2.

Here, in the below circuit I have realized the Boolean expressions for forwarding and reversing the motion of
the motor from the truth table given in the question, then with the help of logic gates given in the question I have
designed the inputs for the corresponding MOSFETS.
 Fig: logic circuit for generating the forward input

Fig: logic circuit to generate Reverse input to the MOSFETS

Fig: Complete Hbridge circuit with PWM control

M1-M3 and M2-M4 in the given figure will turn ON together while changing the state of the motor suddenly
from one state to another state (for example if we are turning the state of the motor from forward to reverse) since
switching of the MOSFETs is associated with the parasitic capacitances associated with it, parasitic capacitances
generate the oscillations and voltage spikes which further changes the switching timings so there’s some time where
both of the mentioned transistors will turn ON. So, to avoid this we have to suppress the voltage spikes, In the H
bridge, if M1-M3 and M2-M4 are turned ON at the same time then it creates a low-resistance path between
power and GND, effectively short-circuiting the power supply. This condition is called ‘shoot-through’
and is an almost guaranteed way to quickly destroy the bridge.
To prevent this, we have to delay the turn-on of the low-side FET by at least as much as the
turn-off time of the high-side FET. The same goes of course for the other transition when we
switch from the low-side to the high-side. This technique has many names, dead-time, shoot-
through protection, no-overlap PWM, but whatever we call it unless we know the turn-off times, we
can’t time this delay properly.
So, the below waveforms are generated externally and supplied to the inputs of the transistors

There’s an IR2112 driver IC, which is used as a gate driver by adding a capacitor to attenuate the
effect of parasitic components and the freewheeling current, suppressing the negative voltage spikes.

We can also use the solution given in the paper at https://patents.google.com/patent/US6147545A/en