VLSI Design

Assignment-2
Sahukari Chaitanya Varun
EE19BTECH11040
November 9, 2021

1 MOSFET Resistance
1.1 Simulation
For measuring the Req , we find the R averaged over the Vds ranging from
Vdd =1.8V to Vdd /2=0.9V . The R at an instant can be found as instantaneous
ratio of voltage across the capacitor and current through the capacitor.
1.1.1 NMOS : W=240nm L=180nm

Figure 1: Circuit Diagram

1
 The netlist for the above circuit is :
M1 Vds Vgs 0 0 n c h t t W=240n , L=180n
V1 Vgs 0 {X}
C1 Vds 0 1p IC =1.8
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
. s t e p param X 0 . 6 1 . 8 0 . 0 1
. t r a n 100u
. i c V( vds )=1.8
. meas TRAN Req AVG (V( vds ) / Id (M1) ) TRIG time=0 TARG V( vds )=0.9
∗ W=240n , L=180n
. backanno
. end
The resulting output of the simulation : Req vs Vdd

Figure 2: Equivalent Resistance variation (W=240nm,L=180nm)

2
1.1.2 NMOS : W=400nm L=180nm

Figure 3: Circuit Diagram

The netlist is :
M1 Vds Vgs 0 0 n c h t t W=400n , L=180n
V1 Vgs 0 {X}
C1 Vds 0 1p IC =1.8
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
. s t e p param X 0 . 6 1 . 8 0 . 0 1
. t r a n 100u
. i c V( vds )=1.8
. meas TRAN Req AVG (V( vds ) / Id (M1) ) TRIG time=0 TARG V( vds )=0.9
∗ W=400n , L=180n
. backanno
. end

3
 The resulting output of the simulation : Req vs Vdd

Figure 4: Equivalent Resistance variation (W=400nm,L=180nm)

1.1.3 PMOS : W=240nm, L=180nm

Figure 5: Circuit Diagram

4
 The netlist is :
V1 Vgs 0 {X}
C1 0 Vds 1p
M1 Vds Vgs 0 0 p c h t t W=240n , L=180n
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
. s t e p param X −1.8 −0.6 0 . 0 1
. t r a n 100u
. i c V( Vds)={X}
. meas TRAN Req AVG (V( vds ) / Id (M1) ) TRIG time=0 TARG V( vds )={X}/2
∗ W=240n , L=180n
. backanno
. end
The resulting output of the simulation : Req vs Vdd

Figure 6: Equivalent Resistance variation (W=240nm,L=180nm)

Note that the graph is drawn for Vgs , hence is negative in the x-axis.

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1.1.4 PMOS : W=400nm, L=180nm

Figure 7: Circuit Diagram

The netlist is :
V1 Vgs 0 {X}
C1 0 Vds 1p
M1 Vds Vgs 0 0 p c h t t W=400n , L=180n
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
. s t e p param X −1.8 −0.6 0 . 0 1
. t r a n 100u
. i c V( Vds)={X}
. meas TRAN Req AVG (V( vds ) / Id (M1) ) TRIG time=0 TARG V( vds )={X}/2
∗ W=400n , L=180n
. backanno
. end

6
 The resulting output of the simulation : Req vs Vdd

Figure 8: Equivalent Resistance variation (W=400nm,L=180nm)

1.2 Comparision with reference table

Figure 9: Reference Values for equivalent resistance

Here the reference is made taking the W/L ratio to be 1.

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 The resulting output is as shown :

Figure 10: Output Values for equivalent resistance in ohms

From the above tables, it can be seen that

• The resulting trend is similar to the given reference trend. The resis-
tance sharply increases as we move towards Vt .

• The resistance for larger W/L ratio is smaller, indicating the inverse
proportionality.

• The equivalent resistance of PMOS is more compared to that NMOS

which can be attributed to lower mobility of holes than electrons.

2 MOSFET Capacitance

Figure 11: Ciruit for study of MOS capacitance

Here Vapplied = VCM + Vo sin(ωt), making I = CVo ωcos(ωt).

For Vo = 1/2πf , we get the gate current peak to be the equivalent capacitance
value. Varying the VCM gives us the CV characteristics. We will consider long
and short channel MOSFETs with L = 10 m and L = 0.18 m respectively.
Both devices have identical W/L of 1.5/2.5.

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2.1 CV characteristics of Long Channel MOSFET
2.1.1 Long Channel CV Characteristics

Figure 12: Circuit Diagram

The corresponding netlist is :

V1 N001 N002 SINE ( 0 0 . 1 5 9m 1k )
M1 0 N001 0 0 n c h t t w=6u l =10u
V2 N002 0 {X}
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
∗ F=1kHz
∗ Long
. s t e p param X −1.8 1 . 8 0 . 2
. t r a n 10m
. meas TRAN C a p a c i t a n c e MAX I g (M1) FROM 2m TO 10m
. backanno
. end

9
Figure 13: Gate Current for sweep in gate voltage(dc)

Figure 14: CV Characteristics for L=10µm and f=1kHz

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2.1.2 Short Channel CV Characteristics

Figure 15: Circuit Diagram

The corresponding netlist is :

V1 N001 N002 SINE ( 0 0 . 1 5 9m 1k )
M1 0 N001 0 0 n c h t t w=114nm l =180nm
V2 N002 0 {X}
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
∗ F=1kHz
∗ Long
. s t e p param X −1.8 1 . 8 0 . 2
. t r a n 10m
. meas TRAN C a p a c i t a n c e MAX I g (M1) FROM 2m TO 10m
. backanno
. end

11
 Figure 16: Gate Current for sweep in gate voltage(dc)

Figure 17: CV Characteristics for L=180 nm and f=1kHz

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2.1.3 CV Characteristics for f=10MHz

Figure 18: Circuit Diagram

The corresponding netlist is :

V1 N001 N002 SINE ( 0 0 . 0 1 5 9 u 10meg )
M1 0 N001 0 0 n c h t t
V2 N002 0 {X}
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
∗ F=10MHz
∗ default
. s t e p param X −1.8 1 . 8 0 . 2
. t r a n 10u
. meas TRAN C a p a c i t a n c e MAX I g (M1) FROM 2u TO 10u
. backanno
. end

13
 Figure 19: Gate Current for sweep in gate voltage(dc)

Figure 20: CV Characteristics for typical nmos at f=10MHz

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2.1.4 CV Characteristics for f=10GHz

Figure 21: Circuit Diagram

The corresponding netlist is :

V1 N001 N002 SINE ( 0 0 . 0 1 5 9 n 10 g )
M1 0 N001 0 0 n c h t t
V2 N002 0 {X}
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
∗ F=10GHz
∗ default
. s t e p param X −1.8 1 . 8 0 . 2
. t r a n 10n
. meas TRAN C a p a c i t a n c e MAX I g (M1) FROM 2n TO 10n
. backanno
. end

15
 Figure 22: Gate Current for sweep in gate voltage(dc)

Figure 23: CV Characteristics for typical nmos at f=10MHz

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2.2 Observations and Comments

Figure 24: Referenc Capacitance Diagram

• All the graphs have similar shape to the reference graph of the gate
capacitance.

• As the capacitance is proportional to the size parameter, long channel

MOSFET has higher capacitance than short channel MOSFET.

• The capacitance value drops as Vgs approaches VT , indicating the dis-

continuity at VT . The fall of slope is larger for long channel than short
channel NMOS.

• For larger frequencies, we see that suitably adjusting the amplitudes

of AC signal, results in normal and identical CV characteristics and
both have low capacitance values. This can be reasoned as, in general
the gate capacitance is resulting from the minority carriers inversion
of the source-drain and depletion capacitance of the bulk. When the
frequency is very high, the rate of inversion of channel cannot follow the
pace of the change. And hence, the capacitance is contributed solely
by the depletion capacitance. So, after a certain high frequency, the
variation of capacitance nearly remains the same.

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3 Inverter Implementations
Given implementations:

Figure 25: Different Inverter Implementations

3.1 Inverter (i):

3.1.1 Static Power when Vin is high
When Vin is high, the NMOS goes to triode finally as Vgs − VT is 1.2V-0.3V,
which is 0.9V, whereas, the capacitor after discharge, makes the Vds ≈ 0V.
So the Vdd is connected to ground through RL and Req of MOS, consuming
static power.

3.1.2 Static Power when Vin is low

When Vin is low, the NMOS enters cut-off, hence making the path between
the supply and ground to be open, hence not consuming any static power.

3.1.3 VOH =1.2V possibility

When Vin is low, i.e, 0V, the NMOS acts like an open switch (cutoff), and the
capacitor in the other path ensures the Vout to fill till 1.2V. Hence, VOH =1.2V
is possible.

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3.1.4 VOL =0V possibility
When Vin is high,i.e, 1.2V, the NMOS is in saturation and has its own RON
resistance, then Vout will the voltage divided input, and not exactly zero.
Hence VOL ̸= 0V.

3.1.5 Dependence of Size of MOS

As we have already seen the effect of equivalent resistance in the case where
Vin is high and the equivalent resistance is itself inversely proportional to the
(W/L) ratio, the size dependence is clearly evident.

3.2 Inverter (ii):

3.2.1 Static Power when Vin is high
When Vin is high, the capacitor discharges in triode region through the bot-
tom nmos to zero. Here the MOS connected to supply remains in saturation
as its Vds > Vgs − VT . Hence we get a path connected from supply to ground
making consumption of static power.

3.2.2 Static Power when Vin is low

When Vin is low, the NMOS near to the supply enters cut-off as Vout ap-
proaches VG -VT =0.9V, hence making the path between the supply and ground
to be open, hence not consuming any static power.

3.2.3 VOH =1.2V possibility

When Vin is low, the bottom NMOS acts as cut-off, and the cap is charged
through the supply MOS. Initially, the VDS =1.2-Vout =1.2 and Vgs -VT =0.9V,
but when the cap starts charging, the Vs builds up, and when VS =Vout =VG -
VT , the supply MOS also enters cut-off. Hence making VOH =0.9̸=1.2.

3.2.4 VOL =0V possibility

When Vin is high,i.e, 1.2V, bottom NMOS has initially VDS =VGS -VT , hence
initially will be in velocity saturation. But then after slight discharge, it
enters triode region as VGS -VT ¿VDS , as VD is decreasing. Hence the cap can
get discharged until there is no further current flow. In the whole process the

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 supply NMOS lies in saturation, except initially. At that stage, the VOL is
dependent on the voltage divider ration RL and RON of NMOS. Hence VOL
̸= 0V.

3.2.5 Dependence of Size of MOS

As we have already seen the effect of equivalent ON resistance, the circuit
needs the size of the devices for functioning.

3.3 Inverter (iii):

3.3.1 Static Power when Vin is high
The given circuit is very much similar to the previous circuit with higher gate
voltage. When Vin is high, the capacitor discharges in triode region through
the bottom nmos to zero. Here the MOS connected to supply remains in
saturation as its Vds = Vgs − VT . Hence we get a path connected from supply
to ground making consumption of static power.

3.3.2 Static Power when Vin is low

When Vin is low, the NMOS near to the supply enters cut-off as Vout ap-
proaches VG -VT =1.2V, hence making the path between the supply and ground
to be open, hence not consuming any static power.

3.3.3 VOH =1.2V possibility

When Vin is low, the bottom NMOS acts as cut-off, and the cap is charged
through the supply MOS. Initially, the VDS =1.2-Vout =1.2 and Vgs -VT =1.2V,
hence unlike the previous case, the voltage completely builds up till 1.2V.
Hence VOH =1.2V is possible.

3.3.4 VOL =0V possibility

When Vin is high,i.e, 1.2V, bottom NMOS has initially VDS =VGS -VT , hence
initially will be in velocity saturation. But then after slight discharge, it
enters triode region as VGS -VT ¿VDS , as VD is decreasing. Hence the cap can
get completely discharged until there is no further current flow. In the whole
process the supply NMOS lies in saturation/triode, except initially. At that

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stage, the VOL is dependent on the voltage divider ration RL and RON of
NMOS. Hence VOL ̸= 0V.

3.3.5 Dependence of Size of MOS

As we have already seen the effect of equivalent ON resistance, the circuit
needs the size of the devices for functioning.

3.4 Inverter (iv): CMOS Inverter

3.4.1 Static Power when Vin is high or Vin is
As we know in a CMOS inverter either cases, either of the MOS is in cut-off.
Hence, there is no path between supply and ground resulting in negligible
static power losses.

3.4.2 VOH =1.2V possibility

As PMOS can pull up the voltages, VOH =1.2V.

3.4.3 VOL =0V possibility

As NMOS can pull down the voltages, VOL =0V.

3.4.4 Dependence of Size of MOS

As the current flowing in the final states(digital) is near to zero(leakage cur-
rents), there is no need of resistance to depict, hence the circuits functionality
is independent of the relative sizes of transistors.

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4 NMOS Inverter - Manual Analysis

Figure 26: NMOS Inverter

Take VT = 0.43V, VDSAT = 0.63V, λ = 0.06V −1 and κn = 115×10−6 A/V 2 .

4.1 VOH , VOL and VM

For VOH , Vin is low, the NMOS remains in cut-off. If the leakage current is
taken to be negligible, then VOH =2.5V.
For VOL , Vin is high, the Vout is nearly grounded, so the NMOS remains in
triode region. Then the current through 75kΩ is corresponding triode current.
Here Vgs =2.5V and hence Vgs − VT =2.07
!
2
2.5 − Vout −6 Vout
= 115 ∗ 10 ∗ 3 ∗ 2.07 ∗ V out −
75 ∗ 103 2

Solving the quadratic gives Vout =0.04632. Hence VOL =46.32mV. For calcu-
lating VM , we need the current through resistor to match exactly with drain
current and Vout =Vin =VM . Then Vgs − VT > Vds , the NMOS remains in the
saturation. Then using the λ, κn and VT gives

2.5 − VM 115 × 10−6 × 3

3
= (VM − 0.43)2 (1 + 0.06 × VM )
75 × 10 2
Computing the cubic, results in VM =0.787V.

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4.2 VIL,VIH and Noise Margins
We know the expressions from the linear approximations as
VM
VIH = VM −
g
VDD − VM
VIL = VM +
g
where g is the slope of Vout vs Vin at VM i.e, (ignoring the channel modulation
effects for easier calculation)
∂Vout
g=
∂Vin
Vout = 2.5 − RL × Ids
 
∂Vout W
= −RL × κn × (Vin − 0.43V )
∂Vin L
where Vin =VM =0.787V, then

g = −75 × 103 × 115 × 10−6 × 3 × (0.787 − 0.43)

=⇒ g = −9.237375
=⇒ VIH = 0.8722V
=⇒ VIL = 0.606V
The noise margins are calculated as

N MH = VOH − VIH

=⇒ N MH = 2.5 − 0.8722 = 1.6278

N ML = VIL − VOL
=⇒ N ML = 0.606 − 0.04632 = 0.55968

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4.3 Peak Gain
As seen earlier the gain is given as
 
∂Vout W
g= = −RL × κn × (Vin − 0.43V )
∂Vin L

For maximum gain, we need to maximise Vin but also stay under saturation.
For boundary condition, consider

Vds = Vgs − VT

Vout = Vin − 0.43

At this point, conserving the current gives

2.5 − Vout 115 × 10−6 × 3 2

= (V in − 0.43)
75 × 103 2
2
2.5 − Vout = 12.9375 × Vout
On solving above equation yields, Vout = 0.4026V , so Vin = 0.8326V. Then
corresponding gain is
 
W
|g| = RL × κn × (Vin − 0.43V )
L

|g| = 75 × 103 × 115 × 10−6 × 3 × 0.4026 = 10.417275

Hence the maximum gain we can extract is nearly 10.417 times the input.

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5 NMOS Inverter - SPICE Simulations
5.1 VTC and Gain

Figure 27: Circuit Diagram

The netlist is given as

V1 N001 0 1 . 8V
R1 N001 Vout 75 k
M1 Vout Vin 0 0 n c h t t W=540nm L=180nm
V2 Vin 0 1 . 8
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
∗ W=540nm L=180nm
. dc V2 0 1 . 8 0 . 0 1
. backanno
. end

25
 Figure 28: VTC for typical NMOS

Figure 29: Gain Plot

The simulated outputs verifies our observations. The gain occurs when
saturation to triode at higher Vin (0.655V,8.5). And VM is nearly around
0.644V, like the calculated case, is near but slightly less than the maximum
gain input.

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5.2 Impact of Load Resistance

Figure 30: Circuit Diagram

Netlist :
V1 N001 0 1 . 8V
R1 N001 Vout {X}
M1 Vout Vin 0 0 n c h t t W=540nm L=180nm
V2 Vin 0 1 . 8
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
∗ W=540nm L=180nm
. dc V2 0 1 . 8 0 . 0 1
. s t e p param X 1k 100 k 1k
; . meas max gain MAX −D(V( vout ) ) TRIG V( Vin)=0 TARG V( Vin )=1.8
; . meas Vt FIND V( Vin ) WHEN V( v i n )=V( vout )
. backanno
. end

27
 Figure 31: Gains at different RL

Figure 32: Variation of VTC wrt RL

28
 Figure 33: Variation of Max Gain wrt RL

Figure 34: Threshold Voltage Variation wrt RL

29
 Observations and Comments :
• The maximum attainable gain increases with the increase in load resis-
tances as VTC curves become more ideal, have sharper slopes, which
also can be seen from the previously derived equations.

• The reasons for this can be attributed to increase noise margins N MH

and N ML and decrease in VOL and VIH .

• And as the curves become ideal, and the VIH also decreases, then VT
would also be expected to decrease as observed from the simulation.

5.3 Rise Time, Fall Time and Average Propogation de-

lay

Figure 35: NMOS Inverter

We can observe, for the fall time, when the capacitor is discharging the
current passes through the load and the NMOS itself which is in triode region
of operation. The effective resistance for this cap here would be

Ref f 1 = RON ||RL

RON RL
Ref f 1 = ≈ RON
RON + RL
Hence the fall time is given as

tf = 2.2 ∗ 0.69ln(Ref f 1 CL )

30
And for the rise time, when the input is low, the NMOS is in cut-off and the
cap charges through only RL from supply. Then in this case

Ref f 2 = RL

tr = 2.2 ∗ 0.69ln(Ref f 2 CL )
As can be observed, Ref f 2 > Ref f 1 , tr > tf . Hence rise and fall times are
unequal. As the fall time is dependent on the resistance offered by the NMOS,
the geometric parameter (W/L) ratio is effecting parameter. For calculating
the propagation delay
tpHL + tpLH
tp =
2
And based on the effective resistances previously analysed

tpHL = 0.69(Ref f 1 CL )

tpLH = 0.69(Ref f 2 CL )
 
(Ref f 1 CL ) + (Ref f 2 CL )
tp = 0.69
2
 
((Ref f 1 + Ref f 2 )CL )
tp = 0.69
2
For the earlier case, we get

tpLH = 0.69(RL CL ) = 155.25ns

For tpHL we need to find the average RON of the NMOS. So we need Ron at
Vout = 2.5V and at Vout = 1.25V. At Vout =2.5, the discharge happens initially
in velocity saturation. From the data, we are given VDSAT =0.63V, the we
can find IDSAT to be 0.39mA. Hence Ron is 6.4kΩ at Vout =2.5V. And at
Vout =1.25V, the NMOS is still in velocity saturation region (Vds =1.25V,Vgs −
V T =2.07,VDSAT =0.63V), hence the Ron at Vout =1.25V is 3.2kΩ. The average
Ron is 4.8kΩ. Then

tpHL = 0.69 ∗ (RON CL ) = 9.936ns.

Hence
155.25 + 9.936
tp = = 82.5ns.
2
The maximum safe operable frequency is fm = 1/(2p ) which is 12.1MHz.

31
 Then the dynamic power consumption is given as

Pdyn = CL VDD ∆V fm = CL VDD (VDD − VOL )fm

=⇒ Pdyn = 0.224mW.

5.3.1 Simulations for 180nm technology

Figure 36: Circuit Diagram

Netlist :
V1 N001 0 1 . 8V
R1 N001 Vout 75 k
M1 Vout Vin 0 0 n c h t t W=540nm L=180nm
V2 Vin 0 PULSE( 0 1 . 8 0 1p 1p 2u 4u )
C1 0 Vout 3p
. model NMOS NMOS
. model PMOS PMOS
. l i b LTspiceXVII \ l i b \cmp\ s t a n d a r d . mos
. i n c l u d e TSMC180 . l i b
∗ W=540nm L=180nm
. t r a n 12u
. meas TRAN t 1 V( Vout ) when V( Vout ) = { 0 . 1 8 } r i s e =1
. meas TRAN t 2 V( Vout ) when V( Vout ) = { 1 . 6 2 } r i s e =1
. meas TRAN t f PARAM ( t3−t 4 )
. meas TRAN t 3 V( Vout ) when V( Vout ) = { 0 . 1 8 } f a l l =1

32
. meas TRAN t 4 V( Vout ) when V( Vout ) = { 1 . 6 2 } f a l l =1
. meas TRAN t r PARAM ( t2−t 1 )
. meas TRAN t 5 V( Vout ) when V( Vout ) = { 0 . 9 } f a l l =2
. meas TRAN t 6 V( Vout ) when V( Vout ) = { 1 . 8 } f a l l =2
. meas TRAN t p h l PARAM ( t6−t 5 )
. meas TRAN t 7 V( Vout ) when V( Vout ) = { 0 . 9 } r i s e =2
. meas TRAN t 8 V( Vout ) when V( Vout ) = { 0 . 0 2 5 9 0 9 8 } CROSS=2
. meas TRAN t p l h PARAM ( t7−t 8 )
. meas TRAN tp PARAM ( t p l h+t p h l ) / 2
. meas TRAN Vol MIN V( Vout ) FROM 0 TO 12u
. backanno
. end

Figure 37: Simulation Output

The rise time and fall time are clearly not same from the above graph.

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 Figure 38: Parameter values

The simulated values nearly correspond to the theoretical values esti-

mated. The slight difference can be reflected because of the voltage supply
difference, and different geometric parameters.

34