DIGITAL INTEGRATED CIRCUIT

DESIGN

Presented By
ANJALI R (2023617026)
1.What is channel length modulation?. Give the drain current expression when the device considering channel length modulation.

Channel length modulation refers to the phenomenon in MOS transistor where the effective length of the conductive channel is actually modulated by the applied, increasing causes the depletion region at the drain junction to grow, reducing the length of the effective channel.The current increases when the length factor L is decreased. The current of the MOS transistor is

an empirical parameter, called the channel-length modulation

2.Draw the stick diagram of 2-input NAND gate

STICK DIAGRAM
3. A PMOS transistor has of -0.4V while the body-effect coefficient equals -0.4. Compute its threshold voltage (V T) for
VSB = -2.5V and = 0.3V.

VT = VT0 + ( - )

=(-0.4)+(-0.4)( -

= -0.4+(-0.4)(1.7606-0.7745)

= -0.4+(-0.4)(0.9861)

= -0.4-0.3944

VT = -0.79444V
4. Determine tpHL for the circuit shown Figure-1 (Given R1 = R2 = R3=R4 = 6.5 KΩ, C1 = C2 = C3=
0.85fF and CL= 3.47fF)

Solution

R1 = R2 = R3=R4 = 6.5 KΩ
C1 = C2 = C3= 0.85fF
CL= 3.47fF
By using elmore model,
tpHL = 0.69{R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3+R4) CL }
tpHL=0.69*123.37*10-12
= 85.1253*10-12
tpHL= 85.1253 ps
5. Give the logical effort of 3 input NOR Gate and 3 input NAND

3 i/p NAND gate

Logical effort =Cin/Cinverter 3 i/p NOR gate

Logical effort = 2+3/3 = 5/3 Logical effort = 2+2+2+1/3 = 7/3

6. Why PMOS is not used in pull down path and NMOS is not used
in pull up path?

 NMOS passes strong 0 and weak 1 (ie)[it passes only[V DD-Vtn]]

 PMOS passes strong 1 and weak 0 (ie)[it passes only |-V tp|)
 Hence NMOS cannot be used in PUN and PMOS cannot be used in PDN.
 PMOS has higher resistance and slower switching activity. Hence cannot be used in PDN.
 NMOS are more efficient at driving signals at low logic level and they provide a low impedance
path to GND when activated .Hence often used in PDN.
 PART B
7.a.i) Derive an expression for drain current ID of an NMOS
transistor in various operating regions.
Cut off Region:
In this region , the Vgs is less than the VT .Hence there is no formation of channel and also zero
current flows from drain to source.
Vgs<VT
ID = 0
Linear Region
Assume now that VGS > VT and that a small voltage, VDS, is applied between drain and source. The voltage difference causes
a current ID to flow from drain to source. At a point x along the channel, the voltage is V(x), and the gate-to-channel
voltage at that point equals VGS – V(x).

Qi(x) = –Cox[VGS – V(x) – VT]

Cox stands for the capacitance per unit area presented by the gate oxide
Cox =
eox= is the oxide permittivity
tox =is the thickness of the oxide
ID = –(x)Qi(x)W
The electron velocity is related to the electric field through a parameter called the mobility
mn(expressed in m2/V×s).

ID dx = mnCoxW(VGS– V – VT)dV
Integrating the equation over the length of the channel L yields the voltage-current relation
of the transistor.

k’n= gain factor kn

Saturation Region:
As the value of the drain-source voltage is further increased, the assumption that the channel
voltage is larger than the threshold all along the channel ceases to hold. This happens
when VGS - V(x) < VT. At that point, the induced charge is zero, and the conducting channel
disappears or is pinched off.
NMOS transistor under pinch-off conditions

The transistor is in the saturation region. The voltage difference over the induced channel (from the
pinch-off point to the source) remains fixed at VGS - VT, and consequently, the current remains
constant (or saturates). Replacing VDS by VGS - VT yields the drain current for the saturation
mode.