EC3058D-VLSI Circuits and Systems

Winter Semester-2020-21
Problem Sheet-1

1. What region of operation are the following transistors in? Assume VDD = 3.3V , VT On =
|VT Op | = 0.5V and MOSTs are long channel type.

2. Sketch IX (roughly) as a function of VX for the following circuits assuming VX varies from 0 to
3V. Assume the MOSTs are of long channel type with negligible channel length modulation.
Assume , VT On = 0.7V , VT Op = −0.8V ,γ = 0.45V −1/2 for nMOS and −0.4V −1/2 for pMOS;
tox = 90Ao ,| − 2φF | = 0.6V

3. The transistor M1 experiences velocity saturation and has the following transistor parameters,
k 0 = 110µAV −2 , VT = 0.4V , VDSAT = 0.6V , (W/L) = (2.5µ/0.25µ), γ = λ = 0. (a) When
R = 10kΩ, find the operating region, VD and VS . (b) When R = 30kΩ, find the operating
region, VD and VS . (c) For the case R = 10kΩ, would VS increase or decrease if λ 6= 0.
Explain qualitatively.

4. Derive the equivalent W/L of the two NMOSTs with W1 /L and W2 /L connected in (i) series
(ii) parallel (Neglect channel length modulation and body bias effects).

5. Find the rise time and fall time of the output of the following circuit. Assume MOSFET to
be long channel type with negligible body bias effect and channel length modulation.

1
 6. Consider a CMOS inverter with VDD = 2.5V and CL = 10f F . The NMOS transistor has
following parameters: velocity saturation voltage VDSAT n = 0.5V , VT n = 0.4V , λn = 0.06V −1
and kn = 120µAV −2 . Find the accurate value of the fall time (tf all ) of this CMOS inverter
if tf all is defined as the time required for the output voltage to drop from V80% level to V20%
level.
7. Design a minimum size CMOS inverter of 0.25µm technology with switching threshold of
1.25V (VDD = 2.5V ).

8. Derive an expression for the switching threshold (VM ) of a CMOS inverter which consists of
long channel MOS transistors. Neglect the effect of channel length modulation.
9. Find VOL , VOH and VM for the given inverter with NMOS load. Assume the nMOS transistors
to be identical and velocity saturated ones. Also find VIL , VIH , N MH and N ML . Assume
0
kn = 115µA/V 2 ; γ = λ = 0.Does this circuit belong to ratioed logic?

10. In a digital IC, a reference inverter (symmetrical delay) has to drive an output pad capacitance
(load capacitance) of 50Cg , where Cg is the gate capacitance of the reference inverter. The
intrinsic delay of the reference inverter is tpo . Assume input and output capacitances of the
reference inverter are equal.
(a) Calculate the delay at the output node if the reference inverter directly drives the load
capacitance.
(b) Design an inverter chain to minimize the delay to the output node. What is the corre-
sponding delay at the output node?
11. In fig.1 M1 and M2 have (W/L) = 10 and negligible channel length modulation. If I1 = 500µA,

(a) Determine VG and I2

(b) What is the largest value of R for which velocity saturation will occur?