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Faculty of Engineering 2 Year Electrical Engineering
Electronics & Comm. Eng. Dept. Fall 2021
Exercise 4
MOSFET
1. [Sedra, Example 5.1] Consider a process technology for which Lmin =0.4 μm, tox =8 nm,
μn =450 𝑐𝑚2 /V·s, and VTH =0.7 V.
(a) Find Cox and 𝑘𝑛′ = 𝜇𝑛 𝐶𝑜𝑥 .
(b) For a MOSFET with W/L =8 μm/0.8 μm, calculate the values of VOV , VGS, and
VDSmin needed to operate the transistor in the saturation region with a dc current ID =
100 μA.
(c) For the device in (b), find the values of VOV and VGS required to cause the device to
operate as a 1k resistor for very small VDS.
3. [Sedra, Example 5.6] Analyze the circuit shown below to determine the voltages at all
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nodes and the currents through all branches. Let VTHN = 1 V and 𝑘𝑛′ (W/L) = 1mA/V .
Neglect the channel-length modulation effect (i.e., assume λ = 0). What is the largest
value that RD can have while the transistor remains in the saturation mode?
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4. [Sedra, Example 5.7] Design the circuit of Fig. 5.25 so that the transistor operates in
saturation with ID =0.5 mA and VD =+3 V. Let the PMOS transistor have VTHP =−1 V
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and 𝑘𝑝′ (W/L) = 1 mA/V . Assume λ = 0.
What is the largest value that RD can have while maintaining saturation-region operation?
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5. [Sedra, Example 7.1] Consider the amplifier circuit shown below. The transistor is
specified to have Vt = 0.4 V, k’n = 0.4 mA/V2, W/L = 10, and λ = 0. Also, let VDD = 1.8
V, RD = 17.5 k, and VGS = 0.6 V.
(a) For vgs = 0 (and hence vds = 0), find VOV , ID, VDS, and Av.
(b) What is the maximum symmetrical signal swing allowed at the drain? Hence, find the
maximum allowable amplitude of a sinusoidal vgs.
7. [Razavi, Problem 6.31] An NMOS device operating in saturation with λ = 0 must provide
a transconductance of 1/(50 Ohm). Assume μnCox = 200 μA/V2, and VTH = 0.4 V.
(a) Determine W/L if ID = 0.5 mA.
(b) Determine W/L if VGS − VTH = 0.5V.
(c) Determine ID if VGS − VTH = 0.5V.
8. [Razavi, Example 7.17] Design a source follower to drive a 50-Ohm load with a voltage
gain of 0.5 and a power budget of 10 mW. Assume μnCox = 100 μA/V2, VTH = 0.5V, λ
= 0, and VDD = 1.8V.
9. [Sedra, Example 14.1] Synthesize a CMOS logic circuit that implements the Boolean
function 𝑌 = 𝐴 + 𝐵(𝐶 + 𝐷).
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