Exercise

Analog Integrated Circuits

EEE 418

MOS Device Physics Problems:

1.

2.

For W/L = 50/0.5, and ID= 0.5 mA, calculate the transconductance and output impedance of both NMOS and PMOS devices. Also, find intrinsic gain, defined as gmr0. Sketch IX and the transconductance of the transistor as a function of VX for each circuit in Fig. 1 as VX varies from 0 to VDD. For part (a), assume VX varies from 0 to 1.5 V.

Fig. 1

3. Sketch VOUT as a function of VIN for each circuit in Fig. 2 as VIN varies from 0 to VDD.

Fig. 2

4. Explain why the structures shown in Fig. 3 cannot operate as current sources even though the transistors are in saturation.

Fig. 3

Single-Stage Amplifiers
1.

In the circuit of Fig. 1, assume (W/L)1 = 50/0.5, (W/L)2 = 50/0.5, and ID1 = ID2 = 0.5 mA when both devices are in saturation. Recall that 1/L. (a) calculate the small signal voltage gain, (b) Calculate the maximum output voltage swing while both devices are saturated.

Fig. 1

In the circuit of Fig. 3.3(a), assume (W/L)1 = 50/0.5, RD = 2 k, and = 0. (a)What is the small-signal gain if M1 is in saturation and ID = 1 mA? (b) What input voltage places M1 at the edge of the triode region? What is the small-signal gain under this condition? (c)What input voltage drives M1 into the triode region by 50 mV? What is the small-signal gain under this condition? 3. Suppose the common-source stage of Fig. 3.3(a) is to provide and output swing from 1 V to 2.5 V. Assume (W/L)1 = 50/0.5, RD = 2 k, and = 0. (a)Calculate the input voltages that yield Vout = 1 V and Vout = 2.5 V. (b) Calculate the drain current and the transconductance of M1 for both cases. (c)How much does the small-signal gain, gmRD, vary as the output goes from 1 V to 2.5 V? 4. Plot the intrinsic gain of the saturated device versus the gate-source voltage if (a) the drain current is constant, (b) W and L are constant. 5. For an NMOS device operating in saturation, plot gm, r0, and gmr0 as the bulk voltage goes from 0 to - while other terminal voltages remain constant. 6. Consider the circuit of Fig. 3.9 with (W/L)1 = 50/0.5, (W/L)2 = 10/0.5. Assume = = 0. (a)At what input voltages is M1 at the edge of the triode region? What is the small-signal gain under this condition? (b) What input voltage drives M1 into the triode region by 50 mV? What is the small-signal gain under this condition?
2.

Fig. 4

7. Sketch Vout versus Vin for the circuits of Fig. 6 and Fig. 7 as Vin varies from 0 to VDD. Identify important transition points.

Fig. 6

Fig. 7

8.