Q1. Measured voltage and current data for a MOSFET are given below.

Determine the type of the

device, and calculate the parameters kn and V.0. Assume = -0.3 V

Q2. Using the parameters given below, calculate the current through two nMOS
transistors in series (see Figure P3.11), when the drain of the top transistor is tied to VDD,
the source of the bottom transistor is tied to Vss= 0 and their gates are tied to VDD. The
substrate is also tied to V.,= 0 V. Assume that WIL = 10 for both transistors. k'= 25uA/V^2 ,VM

= 10 V , = 0.6 v

Q3. The following parameters are given for an nMOS process: t= 500 A substrate doping NA =
11016 cm-3 polysilicon gate doping ND = 1 .10^20cm-3 ,oxide-interface fixed-charge density N =
2*10^10 cm-3 ,(a) Calculate VT for an unimplanted transistor. (b) What type and what
concentration of impurities must be implanted to achieve VT=+2VandVT =-2V?

Q4. For the gate shown in Fig. Pull-up transistor ratio is 5/5

Pull-down transistor ratios are 100/5

Vto= 1.0 V ,y=0.4V^½, . = 0.6V

(a) Identify the worst-case input combination(s) for VOL.

(b) Calculate the worst-case value of VOL. (Assume that all pull-down transistors have the same
body bias and initially, that VOL 5% VDD.)
Q5. A store has one express register and three regular ones. It is the store policy that the
express register be open only when two or more of the other registers are busy. Assume that the
Boolean variables A, B, and C reflect the status of each of the regular registers (1 busy, 0 idle).
Design the logic circuit, with A, B, and C as inputs and F as output, to automatically notify the
manager (by setting F = 1) to open the express register. Present two solutions, the first using only
NAND gates, the second using only NOR gates.

Q6. Calculate VOL, VOH VIL, VIH, NML, and NMH for a two-input NOR gate fabricated with
CMOS technology.

Q7. implement D latch using c-mos technology.

Q8. design a full adder using pass transistor logic and transmission gate logic.
Q9. design a 3-bit even parity generator using dynamic logic.
Q10.Consider the following inverter design problem: Given VDD = 5 V, k ' = 30 uA /V^2, and
Vto= 1 V, design aresistive-load inverter circuit with VOL= 0.2 V. Specifically, determine the (WIL)
ratio of the driver transistor and the value of the load resistor RL that achieve the required VOL.
Q11. Design a resistive-load inverter with R = 1 k ohm, such that VOL = 0.6 V. The
enhancement-type nMOS driver transistor has the following parameters: VDD = 5 .0 V

Vto=1.0v ,uoCox = 22.0 uA/V^2 (a) Determine the required aspect ratio, W/L.

(b) Determine VIL and VIH.

(c) Determine noise margins NML and NMH.