Assignment no.

1. A CMOS inverter with minimum sized transistors has βn =0.2mA/V2, βp =

0.1mA/V2 and Vtn=|Vtp|=0.6V. Assume VDD = 3.3V.
a) What is the inverter gate switching threshold (midpoint) voltage VM?
b) What is the resistance for each transistor using our general expression for
MOSFET resistance in saturation?
c) What are the rise and fall times of this circuit if the parasitic capacitance at the
output is 9fF?
d) If a load capacitance, CL = 25fF is added to the output, what are the new rise
and fall times?
e) What are the propagation delays for this circuit considering both parasitic and
load capacitances?

2. Consider a CMOS inverter fabricated in a 0.25-μmprocess for which

Cox=6 fF/μm2, μnCox =110 μA/V2, μpCox=30 μA/V2, Vtn=–Vtp=0.5 V, and
VDD=2.5V. The W/L ratio of QN is 0.375 μm/0.25 μm, and that for QP is 1.125
μm/0.25 μm. The gate–source and gate–drain overlap capacitances are specified to
be 0.3 fF/μm of gate width. Further, the effective (large-signal) values of drain–
body capacitances are Cdbn=1fF and Cdbp=1fF. The wiring capacitance Cw=0.2fF.
Find tPHL, tPLH , and tP when the inverter is driving an identical inverter.

3. Consider the inverter specified in Problem 2 when loaded with an additional 0.1-
pF capacitance. What will the propagation delay become?