Electronics III

Digital Circuits: CMOS inverter

Dynamic Operation
CMOS logic gates

1
 Dynamic CMOS inverter operation
Load capacitance
Sedra and Smith, Chapter 14, section14.3.2
MOST + interconnect capacitances at drain node wiring

Do

Source is connected to bulk (VSB=0) CjSB negligible

Miller

D
C = 2 CGD1 + 2 CGD2 + CDB1 + CDB2 + CG3 + CG4 + Cw

a
CG3+CG4 = (CGB+CGS+CGD)3 + (CGB+ CGS+ CGD)4
Cw = wiring cap
 Dynamic CMOS inverter operation
Load capacitance

To calculate C:
1.Determine all capacitances from technological parameters
and dimensions (slide notes 1)
2.Determine values of capacitances depending on its region
of operation
3. Determine C from the equation Coal
crude
C = 2 CGD1 + 2 CGD2 + CDB1 + CDB2 + CG3 + CG4 + Cw
Dynamic operation of CMOS inverter
Sedra and Smith, Chapter 14, section14.3

Input signal changes from Low to High

Output changes from High to Low HL
Input signal changes from High to Low
Output changes from Low to High LH
Output takes time to respond to change in input Delay
Input
waveform
Propagation delay tp:
Time difference between 50%
change in input step and 50%
change in output swing
Output
Rise and Fall time tr = tf: waveform

Time difference between 10%

and 90% change
Dynamic operation of CMOS inverter
Pull Down (Pull down the output to low):
Input changes from Low to High Output voltage pulled down from High to Low
Capacitance must discharge from VDD to 0 through Qn and current iDN

Input
waveform

Pull Up (Pull up the output to high):

Output
Input changes from High to Low waveform
Output voltage pulled up from Low to High
Capacitance must charge to VDD VDD
through Qp and current iDP

iDP
0 vo
C
CMOS inverter:
inverter:High-Low transition,
o
Propagation Delayt(Simple
pHL

1. Pull Down: Change input to HIGH (VGS = VDD)

t
Propagation delay tpHL
= time to move from E to M
iDN discharges C through QN
a. From E to F VDSN >(VGS – Vt) QN sat
iDN(0) = k’n(W/2L)n(VDD-Vt)2
DUGS Ubb
At F VDS = VDD- Vt end of saturation region

b. From F to M VDSN < VDD – Vt QN linear

At point M VDS = VDD/2 VDI
V6s VbD Vps
iDN(at M,tpHL)= k’n(W/L)n[(VDD-Vt)VDD/2-1/2(VDD/2)2]

Average discharge current

iDN,av = [iDN(0) + iDN(tpHL)]/2
Charge removed by discharging DQ = iav.t = C.DV low bounln
Discharge interval tpHL = CDV/iDN,av = C(VDD/2)/iDN,av
Im
p e DID
CMOS inverter: Low-High transition, tpLH
Gate Propagation Delay
2. Pull Up: Change input to Low, VGS = 0
Saturation Current
region In PMOS
A B Linear region
C
At t=0

IVtpI

VDD/2

A to B PMOS in saturation region i = iDP(0)

VGS p= -VDD , VDSp = 0 to VGSp -Vtp
B to C PMOS in linear region i = iDP(tpLH)
VGS = -VDD , VDSp –VDD/2 at tpLH

iav = ½[ iDP(0) + iDP(tpLH)] tpLH = C(VDD/2)/iav

tp = (tpHL + tpLH)/2
 Dynamic behavior of CMOS circuits
1st order RC circuit: 1. Pull Down
High to Low transition VDD 0 Discharging C
Natural response Exponential decay with discharging time constant tPD=RPD CL

Output Vout
RPD,equiv

Vini= VDD tpHL

CL
VDD/2

Vfinal=0
GND
t
Natural response (Vfinal =0): Vout = Vinitiale-t/t , Vinitial = VDD

Propagation delay tPLH = time for Vout = 0.5Vswing=VDD/2 , tpLH=tpDln 2 =0.7 tpD
Fall time tf = t0.1 – t0.9 (during fall) , t0.1 Vout = 0.1VDD , t0.9 Vout = 0.9 VDD
 Dynamic behavior of CMOS circuits
1st order RC circuit: 2. Pull Up
Low to High transition at output: Vout = 0 VDD Charging C
Step Response Exponential rise with charging time constant tpU=RPUCL
VDD
VDD Vout
iDP RPU
0 Vfinal= VDD
vo
C Output
VDD/2
CL
Vini=0
tpLH t
Step response: Vout = Vinitial + (Vfinal -Vinitial)(1 – e-t/tpU)
Voltage swing Vswing = Vfinal – Vini = VDD - 0
Propagation delay tPLH = time for Vout=0.5Vswing=VDD/2 tpLH=tpUln 2=0.7
tpU
Rise time tr = t0.9 – t0.1 (during rise), t0.1 Vout = 0.1 VDD, t0.9 Vout = 0.9 VDD
CMOS inverter: Dynamic power dissipation
E
Sedra and Smith, Chapter 14, sections 14.3.4 power I V
1. Static power (rail to rail current) = 0 Epotial Eenemy
(except when switching with NMOS & PMOS ON)
2. Leakage power (current) through 1) diodes, and 2) extremely thin oxide
3. Dynamic power supply current charging the load capacitance
DQ during charging C from 0 to VDD (Low to High) = CDV = CVDD
DV during switching = (VDD -0) = VDD (assuming swing = VDD)
polenedenemy
- Switching energy = DQDV = CVDD2
Power dissipation PD = Energy/unit time = Energy x frequency of switching
poke j h
PD = fCVDD2 green
polled gn
gree
Power x Delay product = PD tp Figure of Merit for the technology
 declare potuel
Logic gate circuits V Ed d
E qv Red
mosh
- Sedra and Smith, Chapter 14, section 14.4

1. Combinational logic circuit

H H

The output Y(t) depends

I(t) Combinational Y(t) = f(I(t)) on present input I(t) only
logic circuit

at capcity
2. Sequential logic circuit store
I(t) Combinational Y(t) = f[I(t), Y(t-1)] indeal
logic circuit

+ - The output Y(t) depends on present

I(t-1) input I(t) and on previous output Y(t-1)
or Y(t-1) Memory
- Must include a memory element
Static logic gate circuits
At every point in time each gate output is connected to either
VDD or GND via a low resistive path (except during switching)

Obeyed in CMOS logic gates

The outputs of the gates assume at all times the value of the
Boolean function implemented by the circuit (ignoring transient
effects during switching periods)

(In contrast to dynamic logic circuits to be studied later)

Combinational CMOS logic gate circuits
OR gate
AND gate NMOS I1
I1 I2
X I2 Y
X Y
Y = X when I1 AND I2 = 1 Y = X when I1 OR I2 = 1
Y = X.(I1. I2) Y = X.(I1 + I2)

PMOS I1
I1 I2
X Y X I2 Y
Y = X when I1 AND I2 = 0
Y = X when I1 OR I2 = 0
I1 . I2 = I1 . I2 = I1 + I2
I1 + I 2 = I 1 . I2
NOR gate NAND gate
CMOS static logic gate circuits
CMOS logic gates are composed of NMOS and PMOS transistors
connected in parallel and in series
1. Pull down NMOS transistors passing a strong 0 (GND) to the output
A
A B OR
AND
B
X Y X Y
Y = X if A AND B
Y = X if A OR B
2. Pull UP PMOS transistors passing a strong 1 (VDD) to the output
A
A B
NAND
NOR
B
X Y X Y
Y = X if A AND B = A + B
Series with inverted inputs Y = X if A OR B = AB
Parallel with inverted inputs
CMOS static logic gate circuits
Pull-up and Pull-down Networks
Generalization of CMOS inverter to more inputs.
The digital circuit is composed of a PUN connected to VDD
in series with PDN connected to ground
Pull-up supplying VDD: PMOS transistor QP
Pull-up network of QP’s (PUN)
Pull-down supplying 0: NMOS transistor QN
Pull-down network of QN’s (PDN)
PDN and of PUN are dual logic networks
i.e. their functions are complementary
No dc current flowing rail to rail

Never allow PUN and PDN to be ON at the same time

PUN ON PDN OFF and PDN ON PUN OFF
Complementary CMOS Logic Style
Duality between PUN is dual to PDN (De Morgan theorems)

NOR A+B=A.B

Dual = NAND A .B = A + B
==================================================================================================================

Static CMOS gates are always inverting

Example: To make an AND gate use a NAND + an Inverter

AND = NAND + INV

 Z
CMOS logic gate circuits
Pull-down Networks (Inverting)
Examples of PDN Wigs

pDN
I I

0
Y=A+B
O
Y=AB
O
Y = A + BC

IIB.is
j NOR NAND
T A Bc

PDN implements the “0” parts of the truth table of the function
CMOS logic gate circuits
Pull-up Networks (Non-inverting)
Examples of PUN

pDN

T AB
Y
ABp
UN
Y AB
D
Y=A+B
F A B Y=AB Y = A(B+C)

Q As
NOR NAND

PUN implements the ONE parts of the truth table of the function
CMOS logic gate circuits
Examples

Two input CMOS NOR gate Y EE

U
Y = A + B (PD) Or Y = A B (PU) I
PDN: NMOS parallel
PUN: PMOS series
I A 413

TO
A B NOR
0 0 1
0 1 0
1 0 0
1 1 0
Common non-inverted
inputs for PDN & PUN

YT A B PON
PDN
YEA 15
CMOS logic gate circuitsI A
I AB
Examples
Two input CMOS NAND gate
Y = A B (PD) Or Y = A + B (PU)
PDN: NMOS series
PUN: PMOS parallel

A B NAND
0 0 1
0 1 1
1 0 1
1 1 0
Common non-inverted
inputs for PDN & PUN
CMOS logic gate circuits
PU/PD Gate Synthesis

Example: Y = A(B + CD)

1. a. Express Y for PDN
Y = A(B + CD)
Or PUN
b. Form PUN from Y using
PDN
inverted inputs but in reality keep inputs
uninverted)

Y = A + B(C + D)
B Doc
2. Use duality of 1) transistors (N P)
and 2) of connections (series parallel)
to form PUN from PDN (of a),
or PDN from PUN (of b)
I A B1 CD PDN
CMOS logic gate circuits B Y A LIB
PU/PD Gate Synthesis of Exclusive OR
“Exclusive OR”: Y = A + B
Y=AB+AB Y=(A + B )( A + B )
Ext
5
=AB+AB
Y

A B a, b
Simplify 2.
path
not
B A valid

b=BB a=AA
GND or
1. 2.
Synthesize PUN from Form PDN From Synthesize PDN from Y
Y using inverted inputs duality with PUN using non-inverted inputs

Slight complexity because Y and Y contain inputs and inverted inputs

Must include two extra inverters to get inverted inputs
CMOS logic gate circuits
Transistor Sizing: Inverters
• Sizing = determining W/L of all nMOS and all pMOS in the circuit

• Sizing affects tpHL and tpLH, load capacitance C and hence PD

• Symmetrical operation requires current matching

- For a basic inverter with (W/L)n = n and (W/L)p = p

We have seen that matching equal charging and discharging currents:

mnCox(W/L)n = mpCox(W/L)p where mn/p = electron/hole mobility

mnn = mpp p = (mn/mp)n p>n because mn > mp

Ratio of p/n will differ in short channel devices….. BUT

For symmetrical operation PMOS always larger than NMOS

CMOS logic gate circuits
Transistor Sizing: Logic gates
Sizing = determining size (W/L) of all nMOS and pMOS’s in the circuit
such that charging/discharging current in the worst situation is at least
same as in single transistor basic inverter
Worst situation = input combination with minimum
charging/discharging current supplied by the circuit VDD
VDD
VDD PUN
Iinv
Iinv ID = ICH3
= Iinv
Y
ICH1
Y
Y ICH3
ICH2
Charging current Worst case: Charging current requires
ICH1 = Iinv Charging current through all PMOS ON RCH=nRQp
RCH= RQp =Rinv only one PMOS ICH2 = Iinv For ICH3 = Iinv
RCH = RQp = Rinv RQp=(1/n)Rinv here n=3
CMOS logic gate circuits
Transistor Sizing: Series connected MOST
All inputs 1, 2, and 3 must be HIGH for ID to flow
ID flows in 3 resistances rDS in series.
1 Q1 rDS1
rDS = 1/(diD/dvDS) 2 Q2 rDS,eq
rDS2
In the linear region
iD ≈ k’(W/L)(VGS – Vt) VDS Low rDS
3 Q3 iD iD rDS3

rDS,lin = 1 proportional to 1 / (W/L)

[k’(W/L)(VGS – Vt)]

In saturation
iD = k’(W/2L)(VGS – Vt)2(1 + lVDS) High rDS

rDS,sat = 1 proportional to 1 / (W/L)

[k’(W/L)l(VGS – Vt)2]

rDS is always proportional to 1/(W/L)

CMOS logic gate circuits
Transistor Sizing: Series connected MOST

1 Q1
rDS is proportional to 1/(W/L) rDS1
rDS,eq

Kenshin
2 Q2 rDS2

3 Q3 iD iD rDS3

rDS,eq = const / (W/L)eq

= rDS1 + rDS2 + rDS3 +..= const [1/ (W/L)1 + 1/ (W/L)2 + 1/ (W/L)3 +..]

(W/L)eq = 1
= 1
1/ (W/L)1 + 1/ (W/L)2 + 1/ (W/L)3 +.. S 1/(W/L)i

For 3 inputs (Q’s with identical W/L, all must be ON) ≡ to inverter (W/L)inv = n
1

o
(W/L)eq = (W/L)inv = n = W/L of each transistor = 3n
3 /( W/L)
Each of Q1, Q2 and Q3 must be 3 times larger than Q of the inverter
CMOS logic gate circuits
Transistor Sizing: Parallel connected MOST
rDS = constant/(W/L)

iD1 iD2 iD3 rDS1 rDS2 rDS3 rDS,eq

1 Q1 2 Q2 3 Q3

3Q’s ON

rDS,eq = const/(W/L)eq depends on the number of ON transistors

1/rDS,eq= S 1/rDS,ON = S 1/ const/(W/L)ON
(W/L)eq = S (W/L)ON IF Q1, Q2 and Q3 ON (W/L)eq = (W/L)1 + (W/L)2 + (W/L)3

For 3 inputs (Q’s have identical W/L) ALL ON to be equivalent to an inverter

with (W/L)inv = n
(W/L)eq = (W/L)inv = 3 W/L = n W/L of each transistor = n/3
Each of Q1, Q2 and Q3 can be as small as 1/3 of Q in equivalent inverter
BUT
CMOS logic gate circuits
Transistor Sizing: Parallel connected MOST

iD1 iD2 iD3 rDS1 rDS2 rDS3 rDS,eq

1 Q1 2 Q2 3 Q3

ALL Q’s NOT NECESSARILY ON at the same time

Design should be done for the worst case with only ONE Q ON
(W/L)eq = (W/L)inv = W/L = n
W/L of Q1, Q2 and Q3 must equal n = W/L of Q of inverter

Series Series vs parallel Parallel

n, p =4

Qi
Q1
≡ ≡
o
n, p =2 n, p =4 n, p =4 n, p =8
n, p =4 Q1 Q2 Qeq
Q2 Qeq
IF Q1 and Q2 ON
CMOS logic gate circuits
Transistor Sizing: 4 I/P NOR Gate
PUN: No worst case, all Q’s must be ON

1/p = 1/pA + 1/pB + 1/pC + 1/pD

If all Q’s are identical: 1/p = 4/pQ pQ = 4p

PDN: Worst case when only ONE Q is ON

nA = n B = n C = n D = n
CMOS logic gate circuits
Transistor Sizing: 4 I/P NAND Gate
PUN: Worst case when only ONE Q is ON

pA = p B = p C = p D = p

PDN: No worst case, all Q’s must be ON

r
1/n = 1/nA + 1/nB + 1/nC + 1/nD
ok
If all Q’s are identical: 1/n = 4/nQ nQ = 4n

Since p > n for matching size of NOR gates is larger than NAND gates
CMOS logic gate circuits
Transistor Sizing: Example
Find W/L for all Q’s of the shown logic gate
Assume that for basic inverter
n = 1.5 and p =5
Channel length L = 0.25 mm.
Logic function: Y = (C + D) B + A
Y = (C D + B) A
PDN: Worst case when only one branch ON
1. Branch A ON and branch B and C or D OFF n =n A
2. Branch A OFF and branch B and C or D ON
Only ONE sub-branch ON (C or D)
B and C in series or B and D in series with neq = n
nB = nC = nD = 2n

PUN: Worst case

1. Branch B and A ON pA = p B = 2 p
2. Branch D and C and A ON pC = pD = pA = 3p
3. Rectify pA and pB : 1/p = 1/pA + 1/pB = 1/3p + 1/pB
n 4. pB = 3p/2

D Areas: PMOS: 3x3.75x0.25+1.875x0.25=3.281 mm2

NMOS: 3x0.75x0.25+0.375x0.25 =0.656 mm2
n r Total area: 3.281+0.656 = 3.937 mm2 ≈ 4 mm2.
CMOS logic gate circuits
Effect of Fan-in and Fan-out on propagation delay
Fan-in: Each inverter at the input has 1 NMOS and 1 PMOS
Each additional input: increase in the chip area
increase the input gate capacitance
Longer delay

Fan-out: High fan out = large number of gates to be driven at output

Higher capacitance at output node
Longer delay

IF the number of inputs is too high fix it to Four and fragment the circuit

More gates will be connected in series More delay

BUT may be less than for one too large gate

Design optimization is an essential task