Homework #8

1. Using the follower circuit shown to the right,

(a) Using Vcc=5V, R=RL=1kΩ,, with all transistors (including Q3) identical.
Assume VBE=0.7V, VCEsat=0.3V, and β to be very large. For linear
operation, what are the upper and lower limits of output volt
voltage, and the
corresponding inputs?
(b) Use ±9V
9V supplies, provide a design capable of ±7V outputs with a 1kΩ
load, using the smallest possible total supply current. You are provided
with four identical, high β BJTs and a resistor of your choice.
(a)

(b)

Fall 2010 1
 Homework #8
2. Use I=100mA and RL=100Ω. The output voltage is an 8V peak sinusoid, find the following. Ignore the loss in Q3 and
R. Assume VCEsat is nearly zero. Find the power efficiency in each case: Vcc=16V, 12V, 10V, and 8V.

3. A class B output stage is required to deliver an average power of 100W into a 16Ω load. The power supply should be
4V greater than the corresponding peak sine wave output voltage. The input signal is a sine wave. Determine the
following:
(a) power supply voltage required (to the nearest volt in the appropriate direction)
(b) the peak current from each supply
(c) the total supply power
(d) the power conversion efficiency
(e) the maximum possible power dissipation in each transistor
(a)
(d)

(e)

(b)

(c)

Fall 2010 2
 Homework #8
o o
5. A particular transistor has a power rating at 25 C of 200mW, and a maximum junction temperature of 150 C.
(a) What is its thermal resistance?
o
(b) What is its power rating when operated at an ambient temperature of 70 C?
(c) What is its junction temperature when dissipating 100mW at an ambient temperature of 50oC?

o
6. A power transistor is specified to have a maximum junction temperature of 130 C. When the device is operated at
o
this junction temperature with a heat sink, the case temperature is found to be 90 C. The case is attached to the heat
o o
sink with a bond having a thermal resistance θCS=0.5 C/W and the thermal resistance of the heat sink θSA=0.1 C/W. If
o
the ambient temperature is 30 C what is the power being dissipated in the device? What is the thermal resistance of
the device, θJC, from junction to case?

Fall 2010 3
 Homework #8

Use these two circuits for Problems 7-10.

7. A particular design of the two-stage

stage CMOS operational amplifier shown above utilizes the ±1V
1V power supplies. All
transistors are operated at overdrive voltages of 0.15V magnitude. The process technology provides devices with
Vtn=|Vtp|=0.45V. Find the input common--mode range and the range allowed for vo.

should be VICM>=-0.85V

8. Use the following device geometries:

Transistor Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
W/L (µm/µm) 30/0.5 30/0.5 10/0.5 10/0.5 60/0.5 W/0.5 60/0.5 60/0.5
2 2
Let IREF=225µA, |Vt|=0.75V, µnCox=180µA/VA/V , µpCox=60µA/V , |VA|=9V, VDD=VSS=1.5V. Determine the width of Q6, W,
he op amp will not have a systematic offset voltage. Then, for all devices, evaluate ID, |Vov|,
that will ensure that the
|VGS|, gm and ro. Provide your results in a table. Also find A1, A2, and the dc open loop voltage gain, the input common
mode range, and the output voltage range.
ange. Neglect the effect of VA on the bias currents.

Fall 2010 4
 Homework #8

Q K(µA/V2) I(µA) Vov(V) VGS(V) gm(mA/V) ro(kΩ)

Q1 60 112.5 0.25 1 0.9 80
Q2 60 112.5 0.25 1 0.9 80
Q3 180 112.5 0.25 1 0.9 80
Q4 180 112.5 0.25 1 0.9 80
Q5 60 225 0.25 1 1.8 40
Q6 180 225 0.35 1.1 1.285 40
Q7 60 225 0.25 1 1.8 40
Q8 60 225 0.25 1 1.8 40

Fall 2010 5
 Homework #8
9. A particular implementation of the CMOS amplifier (shown above) provides Gm1=0.3mA/V, Gm2=0.6mA/V,
ro2= ro4 =222kΩ, ro6= ro7 =111kΩ and C2=1pF.
(a) Find the frequency of the second pole, fp2.
(b) Find the value of the resistance R which when placed in series with CC causes the transmission zero to be located at
s=∞.
(c) With R in place, as in (b), find the value of CC that results in the highest possible value of ft while providing a phase
margin of 80o. What value of ft is realized? What is the corresponding frequency of the dominant pole?
(d) To what value should CC be changed to double the value of ft? At this new value of ft,, what is the phase shift of just
the part for this new value? To reduce this part of the phase margin to 10o and thus obtain an 80o phase margin, what
value should R be changed to?

fz=ft/0.166=33.7MHz/0.166=203MHz
fz=1/(2πCc[R-1/Gm2]) solving for R=1/Gm2+1/(2π*1.4e-12*203M)=2.2kΩ
Ω

10. A CMOS op amp with the topology above is designed to provide Gm1=1mA/V and Gm2=5mA/V.
(a) Find the value of CC that results in ft =100MHz.
(b) What is the maximum value that C2 can have while achieving a 70o phase margin?

Fall 2010 6
 Homework #8

Fall 2010 7