CH 13 Power Amplifier Output Stages and Classes

Chapter 13 Output Stages and Power Amplifiers
 13.1 General Considerations

 13.2 Emitter Follower as Power Amplifier
 13.3 Push-Pull Stage
 13.4 Improved Push-Pull Stage
 13.5 Large-Signal Considerations
 13.6 Short Circuit Protection
 13.7 Heat Dissipation
 13.8 Efficiency
 13.9 Power Amplifier Classes
1
Why Power Amplifiers?
 Drive a load with high power.
 Cell phone needs 1W of power at the antenna.
 Audio system needs tens to hundreds Watts of power.
 Ordinary Voltage/Current amplifiers are not equipped for

such applications
CH 13 Output Stages and Power Amplifiers 2

Chapter Outline

Power Amplifier Characteristics
 Experiences small load resistance.
 Delivers large current levels.
 Requires large voltage swings.
 Draws a large amount of power from supply.
 Dissipates a large amount of power, therefore gets “hot”.

Power Amplifier Performance Metrics
 Linearity
 Power Efficiency
 Voltage Rating

Emitter Follower Large-Signal Behavior I
 As Vin increases Vout also follows and Q1 provides more current.

Emitter Follower Large-Signal Behavior II
 However as Vin decreases, Vout also decreases, shutting off Q1

and resulting in a constant Vout.
Example: Emitter Follower
 Vout  1
Vin  VT ln   I1    Vout
 RL  IS 
Vin  0.5V  Vout  211mV
I C1
Vin  VT ln   IC1  I1  RL
IS
I C1  0.01I1  Vin  390mV

Linearity of an Emitter Follower
 As Vin decreases the output waveform will be clipped,

introducing nonlinearity in I/O characteristics.

Push-Pull Stage
 As Vin increases, Q1 is on and pushes a current into RL.

 As Vin decreases, Q2 is on and pulls a current out of RL.
I/O Characteristics for Large Vin
Vout=Vin-VBE1 for large +Vin

Vout=Vin+|VBE2| for large -Vin
 For positive Vin, Q1 shifts the output down and for negative Vin,
Q2 shifts the output up.

Overall I/O Characteristics of Push-Pull Stage
 However, for small Vin, there is a dead zone (both Q1 and Q2 are
off) in the I/O characteristic, resulting in gross nonlinearity.
Small-Signal Gain of Push-Pull Stage
 The push-pull stage exhibits a gain that tends to unity when

either Q1 or Q2 is on.
 When Vin is very small, the gain drops to zero.
Sinusoidal Response of Push-Pull Stage
 For large Vin, the output follows the input with a fixed DC
offset, however as Vin becomes small the output drops to zero
and causes “Crossover Distortion.”

Improved Push-Pull Stage
VB=VBE1+|VBE2|
 With a battery of VB inserted between the bases of Q1 and Q2,

the dead zone is eliminated.

Implementation of VB
 Since VB=VBE1+|VBE2|, a natural choice would be two diodes in

series.
 I1 in figure (b) is used to bias the diodes and Q1.
Example: Current Flow I
I in  I1  I B1  I B 2
If Vout=0 & β1=β2>>1

=> IB1=IB2
Iin

Example: Current Flow II
VD1≈VBE → Vout≈Vin
If I1=I2 & IB1≈IB2

→ Iin=0 when Vout=0

Addition of CE Stage
 A CE stage (Q4) is added to provide voltage gain from the input to

the bases of Q1 and Q2.
Bias Point Analysis
VA=0 Vout=0
IC1=[IS,Q1/IS,D1]×[IC3]
 For bias point analysis, the circuit can be simplified to the one
on the right, which resembles a current mirror.
 The relationship of IC1 and IQ3 is shown above.
Small-Signal Analysis
AV=-gm4(rπ1||r π2)(gm1+gm2)RL
 Assuming 2rD is small and (gm1+gm2)RL is much greater than 1,

the circuit has a voltage gain shown above.
Output Resistance Analysis
1 rO 3 || rO 4
Rout  
g m1  g m 2 ( g m1  g m 2 )( r 1 || r 2 )
 If β is low, the second term of the output resistance will rise,

which will be problematic when driving a small resistance.
Example: Biasing
CE AV=5
Output Stage AV=0.8
RL=8Ω
βnpn= 2βpnp=100
IC1≈IC2
1
g m1  g m 2 
2
1
g m1  g m 2   4 
I C1  I C 2  6.5mA
r 1 || r 2  133
I C 3  I C 4  195 A
Problem of Base Current
 195 µA of base current in Q1 can only support 19.5 mA of collector

current, insufficient for high current operation (hundreds of mA).

Modification of the PNP Emitter Follower
1
Rout 
  2  1 g m3
 Instead of having a single PNP as the emitter-follower, it is now
combined with an NPN (Q2), providing a lower output resistance.

Example: Input Resistance
 
1  RL 
iin   vin  vin 
r 3  1 
 RL  
   2  1 gm3 
rin  3 (  2  1) RL  r 3
Additional Bias Current
 I1 is added to the base of Q2 to provide an additional bias current

to Q3 so the capacitance at the base of Q2 can be
charged/discharged quickly.
Example: Minimum Vin
Min Vin≈0 Min Vin≈VBE2

Vout≈|VEB2| Vout≈|VEB3|+VBE2
HiFi Design
 Using negative feedback, linearity is improved, providing

higher fidelity.
Short-Circuit Protection
 Qs and r are used to “steal” some base current away from Q 1 when
the output is accidentally shorted to ground, preventing short-
circuit damage.
Emitter Follower Power Rating
 VP 
Pav  I1  VCC  
 2 
Pav ,max  T1VCC
 Maximum power dissipated across Q1 occurs in the absence of

a signal.
Example: Power Dissipation
Avg Power Dissipated in I1

1 T

PI 1   I1 V p sin t  VEE dt
T 0

PI 1   I1VEE

Push-Pull Stage Power Rating
2
VP  VCC VP  VCC
Pav     Pav ,max 
RL   4   2 RL
 Maximum power occurs between Vp=0 and 4Vcc/π.

Example: Push-Pull Pav
VP  VCC VP 
Pav     If Vp = 4VCC/π → Pav=0
RL   4 
Impossible since Vp cannot go
above supply (VCC)
Heat Sink
 Heat sink, provides large surface area to dissipate heat from the chip.

Thermal Runaway Mitigation
I D1I D 2 I C1 I C 2

I S , D1I S , D 2 I S ,Q1I S ,Q 2
 Using diode biasing prevents thermal runaway since the

currents in Q1 and Q2 will track those of D1 and D2 as long as
theie Is’s track with temperature.
Efficiency
Pout

Pout  Pckt
Emitter Follower Push-Pull Stage

VP2 2 RL VP2 2 RL
 EF   PP 
VP2 2 RL  I1  2VCC  VP 2  VP2 2 RL  2 I1  VCC /   VP 4 
VP 
 EF   PP  VPVCC I1=VP/RL
4VCC I1=VP/RL 4
 Efficiency is defined as the average power delivered to the load

divided by the power drawn from the supply
Example: Efficiency
Emitter Follower Push-Pull

VP=VCC/2 I1=(VP/RL)/β
1 1 VP
 
15 4 VCC   VP 
Power Amplifier Classes
Class A: High linearity, low efficiency
Class B: High efficiency, low linearity
Class AB: Compromise between

Class A and B

Chapter 14 Analog Filters

 14.2 First-Order Filters
 14.3 Second-Order Filters
 14.4 Active Filters
 14.5 Approximation of Filter Response
40
Outline of the Chapter
CH 14 Analog Filters 41
Why We Need Filters
 In order to eliminate the unwanted interference that

accompanies a signal, a filter is needed.
Filter Characteristics
 Ideally, a filter needs to have a flat pass band and a sharp roll-
off in its transition band.
 Realistically, it has a rippling pass/stop band and a transition
band.
Example: Filter I
Given: Adjacent channel Interference is 25 dB above the signal
Design goal: Signal to Interference ratio of 15 dB
Solution: A filter with stop band of 40 dB
Example: Filter II
Given: Adjacent channel Interference is 40 dB above the signal
Design goal: Signal to Interference ratio of 20 dB
Solution: A filter with stop band of 60 dB at 60 Hz
Example: Filter III
 A bandpass filter around 1.5 GHz is needed to reject the

adjacent Cellular and PCS signals.
Classification of Filters I
Classification of Filters II
Continuous-time Discrete-time
Classification of Filters III
Passive Active
Summary of Filter Classifications
Filter Transfer Function
A B
 Filter a) has a transfer function with -20dB/dec roll-off

 Filter b) has a transfer function with -40dB/dec roll-off, better
selectivity.
General Transfer Function
 s  Z1   s  Z 2    s  Z m  Zm=m’th zero
H (s)  
 s  P1   s  P2    s  Pm  Pn =n’th pole
Pole-Zero Diagram
Position of the Poles
Poles on the RHP Poles on the jω axis Poles on the LHP

Unstable Oscillatory Decaying
(no good) (no good) (good)
Imaginary Zero
 Imaginary zero is used to create a null at certain frequency.
Sensitivity
P dP dC P=Parameter
SC 
P C C=Component
 Sensitivity measures the variation of a filter parameter due to

variation of a filter component.
Example: Sensitivity
0  1 /  R1C1 
d 0 1
 2
dR1 R1 C1
d 0 dR1

0 R1
S R10  1
First-Order Filters
s  z1
H ( s)  
s  p1
 First-order filters are represented by the transfer function

shown above.
 Low/high pass filters can be realized by changing the relative
positions of poles and zeros.
Example: First-Order Filter I
R 2 C2 < R 1 C1 R 2 C 2 > R 1C 1
Example: First-Order Filter II
CH 14 Analog Filters R2C2 < R1C1 R2C2 > R1C1 60

Second-Order Filters
 s2   s  
H (s) 
2 n
s  s  n2
Q
n 1
p1,2    jn 1 
2Q 4Q 2
 Second-order filters are characterized by the “biquadratic”

equation with two complex poles shown above.
Second-Order Low-Pass Filter
2 2
H ( j )  2
 n 
 
2 α=β=0
n2  2
 
Q 
Example: Second-Order LPF
Q3
Q / 1  1/(4Q 2 )  3
n 1  1/(2Q 2 )  n
Second-Order High-Pass Filter
2
s
H (s) 
2 n
s  s  n2 β=γ=0
Q
Second-Order Band-Pass Filter
s
H (s) 
2 n
s  s  n2 α=γ=0
Q
Example: -3-dB Bandwidth
R1L1s
Z2 
R1L1C1s 2  L1s  R1
LC Realization of Second-Order Filters
L1s
Z1 
L1C1s 2  1
 An LC tank realizes a second-order band-pass filter with two
imaginary poles at ±j/(L1C1)1/2 , which implies infinite
impedance at ω=1/(L1C1)1/2.
Example: Tank
 ω=0, the inductor acts as a short.

 ω=∞, the capacitor acts as a short.
RLC Realization of Second-Order Filters
R1L1s
Z2 
R1L1C1s 2  L1s  R1
1 1 L
p1,2   j 1  21
2 R1C1 L1C1 4 R1 C1
 With a resistor, the poles are no longer pure imaginary which

implies there will be no infinite impedance at any ω.
Voltage Divider Using General Impedances
Vout ZP
( s) 
Vin ZS  ZP
Low-pass High-pass Band-pass

Low-pass Filter Implementation with Voltage Divider
Vout R1
 s  2
Vin R1C1L1s  L1s  R1
Example: Frequency Peaking
Vout R1
 s 
Vin R1C1L1s 2  L1s  R1
1
Q Peaking exists
2 Voltage gain larger than unity
Low Pass Circuit Comparison
Good Bad
 The circuit on the left has a sharper roll-off at high frequency

than the circuit on the right.
High-pass Filter Implementation with Voltage Divider
Vout L1C1R1s 2
 s 
Band-pass Filter Implementation with Voltage Divider
2
Vout L1s
 s 
Sallen and Key (SK) Filter: Low-Pass
Vout 1
 s 
Vin R1R2C1C2 s 2   R1  R2  C2 s  1
1 C 1
Q R1R2 1 n 
R1  R2 C2 R1R2C1C2
 Sallen and Key filters are examples of active filters. This
particular filter implements a low-pass, second-order transfer
function.
Sallen and Key (SK) Filter: Band-pass
R3
1
Vout R4
 s 
Vin 2  R3 
R1R2C1C2 s   R1C2  R2C2  R1 C1  s  1
 R4 
Example: SK Filter Poles
C1=C2
R1=R2
Sensitivity in Band-Pass SK Filter
1  R2C2 
S Rn  S Rn  SCn  SCn  SCQ   SCQ
1
   Q  
R1C2

1 2 1 2
2 1 2
2  R1C1 R2C1 
1 R2C2 R1C1
S RQ   S RQ   Q S KQ  QK K=1+R3/R4
1 2
2 R1C1 R2C2
Example: SK Filter Sensitivity I
R1  R2  R
C1  C2  C
1 1
S RQ   S RQ  
1 2
2 3 K
1 2
SCQ   SCQ  
1 2
2 3 K
K
S KQ 
3 K
Example: SK Filter Sensitivity II
Q2
K 2
R2C2 3
  S RQ  1
R1C1 4 1
R1C1 1 Q 5
  SC 
R2C2 8 1
4
8
S KQ 
CH 14 Analog Filters
1.5 81
Integrator-Based Biquads
Vout  s2 n 1 n2
 s  Vout  s   Vin  s   . Vout  s   2 Vout  s 
Vin 2 n Q s s
s  s  n2
Q
 It is possible to use integrators to implement biquadratic
transfer functions.
 The block-diagram above illustrates how.
KHN Biquads
n 1 n2
Vout  s   Vin  s   . Vout  s   2 Vout  s 
Q s s
R5  R6  n R4 1 R6 1
 1    . n2  .
R4  R5  R3  Q R4  R5 R1C1 R3 R1R2C1C2
Versatility of KHN Biquads
High-Pass
Vout  s2
 s  
Vin s 2  n s  n2
Q
Band-Pass Low-Pass
VX  s2 1 VY  s2 1
 s  
.  s  
. 2
Vin Vin
s 2  n s  n2 R1C1s s 2  n s  n2 R1R2C1C2 s
Q Q
Sensitivity in KHN Biquads
S Rn, R ,C ,C , R , R , R , R  0.5 S RQ , R ,C ,C  0.5

1 2 1 2 4 5 3 6
1 2 1 2
Q R3  R6 R2C2 R5
S RQ , R 
2 1  R5 R 3 R6 R1C1
S RQ , R  1
R4  R5
3 6
4 5
R4
Tow-Thomas Biquad
Vout RRR C2 s VY R3 R4 1
 2 3 4.  .
Vin R1 R2 R3 R4C1C2 s 2  R2 R4C2 s  R3 Vin R1 R2 R3 R4C1C2 s 2  R2 R4C2 s  R3
Band-Pass Low-Pass
Example: Tow-Thomas Biquad
1 1 R2 R4C2
n  Q
R2 R4C1C2 R3 C1
Adjusted by R2 or R4 Adjusted by R3
Differential Tow-Thomas Biquads
 By using differential integrators, the inverting stage is

eliminated.
Simulated Inductor (SI)
Z1Z 3
Z in  Z5
Z2Z4
 It is possible to simulate the behavior of an inductor by using
active circuits in feedback with properly chosen passive
elements.
Example: Simulated Inductor I
2
Zin  RX RY Cs
 By proper choices of Z1-Z4, Zin has become an impedance that

increases with frequency, simulating inductive effect.
Example: Simulated Inductor II
Z1  Z 2  Z3  RY
1
Z4 
Cs
Zin  RX RY2Cs 91
High-Pass Filter with SI
Vout L1s 2
 s 
 With the inductor simulated at the output, the transfer function

resembles a second-order high-pass filter.
Example: High-Pass Filter with SI
 RY 
Node 4 is also an output node V4  Vout 1  
 RX 
Low-Pass Filter with Super Capacitor
1
Zin 
Cs  RX Cs  1
Vout Z in 1
 
Vin Zin  R1 R1RX C 2 s 2  R1Cs  1
Low-Pass
Example: Poor Low Pass Filter
V4  Vout  2  RX Cs 
 Node 4 is no longer a scaled version of the Vout. Therefore the

output can only be sensed at node 1, suffering from a high
impedance.
Frequency Response Template
 With all the specifications on pass/stop band ripples and

transition band slope, one can create a filter template that will
lend itself to transfer function approximation.
Butterworth Response
1
H ( j ) 
2n
 
1  
 0 
ω-3dB=ω0, for all n
 The Butterworth response completely avoids ripples in the

pass/stop bands at the expense of the transition band slope.
Poles of the Butterworth Response
j  2k  1 
pk  0 exp exp  j   , k  1, 2, , n
2  2n 
CH 14 Analog Filters 2nd-Order nth-Order 98

Example: Butterworth Order
2n
 f2 
   64.2
 f1 
f 2  2 f1
n=3
 The Butterworth order of three is needed to satisfy the filter

response on the left.
Example: Butterworth Response
 2 2  RC section
p1  2 *(1.45MHz ) *  cos  j sin 
 3 3 
2nd-Order SK
 2 2 
p3  2 *(1.45MHz ) *  cos  j sin 
 3 3  p2  2 *(1.45MHz )
Chebyshev Response
1
H  j  
2 2  
1  Cn  

 0
Chebyshev Polynomial
 The Chebyshev response provides an “equiripple” pass/stop

band response.
Chebyshev Polynomial
Chebyshev Polynomial for Resulting Transfer function for

n=1,2,3 n=2,3
   1  
Cn    cos  n cos  ,   0

 0  0 
 1  
 cosh  n cosh  ,   0
  0 
102
Example: Chebyshev Attenuation
1
H  j  
2
   3 
1  0.329  4    3 
2
  0  0 

ω0=2π X (2MHz)
 A third-order Chebyshev response provides an attenuation of

-18.7 dB a 2MHz.
103
Example: Chebyshev Order
 Passband Ripple: 1 dB
 Bandwidth: 5 MHz
 Attenuation at 10 MHz: 30 dB
 What’s the order?
1
 0.0316
 n cosh 2 
2 2 1 n>3.66
1  0.509 cosh

Example: Chebyshev Response
pk  0 sin
 2k  1  sinh  1 sinh 1 1   j  2k  1  cosh  1 sinh 1 1 
 0 cos
2n n   2n

n  
K=1,2,3,4
p1,4  0.1400  0.983 j0 p2,3  0.3370  0.407 j0
SK1 SK2
Chapter 15 Digital CMOS Circuits

 15.2 CMOS Inverter
 15.3 CMOS NOR and NAND Gates
106
Chapter Outline
CH 15 Digital CMOS Circuits 107

Inverter Characteristic
_
XA
 An inverter outputs a logical “1” when the input is a logical “0”

and vice versa.
NMOS Inverter
1
Ron1 
W
nCox (VDD  VTH )
L
 The CS stage resembles a voltage divider between RD and Ron1

when M1 is in deep triode region. It produces VDD when M1 is off.
Transition Region Gain
Infinite Transition Region Gain Finite Transition Region Gain
 Ideally, the VTC of an inverter has infinite transition region

gain. However, practically the gain is finite.

Example: Transition Gain
 Transition Region: 50
mV
 Supply voltage: 1.8V
V0 – V2: Transition Region 1.8

Av   36
0.05

Logical Level Degradation
 Since real power buses have losses, the power supply levels at
two different locations will be different. This will result in
logical level degradation.
Example: Logic Level Degradation
Supply B=1.675V Supply A=1.8V
V  5 A  25m  125mV

The Effects of Level Degradation and Finite Gain
 In conjunction with finite transition gain, logical level

degradation in succeeding gates will reduce the output swings
of gates.
Small-Signal Gain Variation of NMOS Inverter
 As it can be seen, the small-signal gain is the largest in the

transition region.

Above Unity Small-Signal Gain
 The magnitude of the small-signal gain in the transition region

can be above 1.

Noise Margin
 Noise margin is the amount of input logic level degradation that

a gate can handle before the small-signal gain becomes -1.

Example: NMOS Inverter Noise Margin
1
1: NM L  VIL  W
 VTH
nCox RD
L
1 W
Vout  VDD  nCox RD  2  Vin  VTH  Vout  Vout
2 

2 L
1 V V Vin=VIH
Vout   in TH
W 2
2 nCox RD
L
CH 15 Digital CMOS Circuits 2: NM H  VDD  VIH 118
Example: Minimum Vout
19
RD 
W
nCox  VDD  VTH 
L
 To guarantee an output low level that is below 0.05V DD, RD is

chosen above.
Dynamic Behavior of NMOS Inverter Gates
 Since digital circuits operate with large signals and experience

nonlinearity, the concept of transfer function is no longer
meaningful. Therefore, we must resort to time-domain analysis to
evaluate the speed of a gate.
 It usually takes 3 time constants for the output to transition.
Rise/Fall Time and Delay

Example: Time Constant
19 L2
  RD C X 
n  VDD  VTH 
 Assuming a 5% degradation in output low level, the time

constant at node X is shown above.
Example: Interconnect Capacitance
Wire Capacitance per Mircon: 50x10-18 F/µm
Total Interconnect Capacitance: 15000X50x10-18 =750 fF
Equivalent to 640 MOS FETs with W=0.5µm, L=0.18µm, Cox =13.5fF/µm2

Power-Delay Product
2
PDP  VDD CX
 The power delay product of an NMOS Inverter can be loosely

thought of as the amount of energy the gate uses in each
switching event.
Example: Power-Delay Product
TPLH  3RD C X
PDP   I DDVDD   3RDC X 
2
PDP  3VDDWLCox
Drawbacks of the NMOS Inverter
 Because of constant RD, NMOS inverter consumes static power

even when there is no switching.
 RD presents a tradeoff between speed and power dissipation.

Improved Inverter Topology
 A better alternative would probably have been an “intelligent”

pullup device that turns on when M1 is off and vice versa.

Improved Falltime
 This improved inverter topology decreases falltime since all of

the current from M1 is available to discharge the capacitor.

CMOS Inverter
 A circuit realization of this improved inverter topology is the

CMOS inverter shown above.
 The NMOS/PMOS pair complement each other to produce the
desired effects.
CMOS Inverter Small-Signal Model
vout
   g m1  g m 2   rO1 || rO 2 
vin
 When both M1 and M2 are in saturation, the small-signal gain is

shown above.
Switching Threshold
 The switching threshold (V inT) or the “trip point” of the inverter is

when Vout equals Vin.
 If VinT =Vdd/2, then W2/W1=µn/µp
CMOS Inverter VTC

Example: VTC
W2
 As the PMOS device is made stronger, the VTC is shifted to the

right.

Noise Margins
2 a  Vdd  VTH 1  VTH 2   Vdd  aVTH 1  VTH 2

VIL 
 a  1 a3 a 1
NML =VIL
VIL is the low-level input voltage
at which (δVout/ δVin)=-1
2a  Vdd  VTH 1  VTH 2   Vdd  aVTH 1  VTH 2

NMH =Vdd-VIH VIH 
 a  1 1  3a a 1
VIH is the high-level input voltage

at which (δVout/ δVin)=-1
W 
n  
 L 1
a
W 
p  
 L 2
VIL of a Symmetric VTC
2 a  VDD  2VTH 1   a  3 VDD   a  1 VTH 1 

VIL 
 a  1 a3
Symmetric VTC: a=1
3 1
VIL  VDD  VTH 1
8 4

Noise Margins of an Ideal Symmetric VTC
VDD
NM H ,ideal  NM L,ideal 
2

Floating Output
VTH 1  VDD / 2
VTH 2  VDD / 2
 When Vin=VDD/2, M2 and M1 will both be off and the output floats.
Charging Dynamics of CMOS Inverter
 As Vout is initially charged high, the charging is linear since M 2 is in

saturation. However, as M2 enters triode region the charge rate
becomes sublinear.
Charging Current Variation with Time
 The current of M2 is initially constant as M2 is in saturation. However

as M2 enters triode, its current decreases.

Size Variation Effect to Output Transition
 As the PMOS size is increased, the output exhibits a faster

transition.

Discharging Dynamics of CMOS Inverter
 Similar to the charging dynamics, the discharge is linear when M 1

is in saturation and becomes sublinear as M1 enters triode region.

Rise/Fall Time Delay
Rise Time Delay

CL  2 VTH 2  V 
TPLH    ln  3  4 TH 2  
W  V V  VDD  
 p Cox   VDD  VTH 2   DD TH 2
 L 2
Fall Time Delay

CL  2 VTH 1  VTH 1  
TPHL    ln  3  4 
W  V V  VDD  
nCox   VDD  VTH 1   DD TH 1
 L 1

Example: Averaged Rise Time Delay
1 W 
  p Cox    VDD  VTH 2 
2
I AVG
4  L 2
CL VDD / 2   VDD  VTH 2 

TPLH 2  .
W  VDD  VTH 2
 p Cox    VDD  VTH 2 
 L 2
4
TPLH 2  Ron 2CL
3

Low Threshold Improves Speed
1st Term
CL  2 VTH 2 /1  V 
TPLH / HL    ln  3  4 TH 2 /1  
W  V V  VDD  
 p / nCox   VDD  VTH 2 /1   DD TH 2 /1
 L  2 /1
2nd Term
 The sum of the 1st and 2nd terms of the bracket is the smallest
when VTH is the smallest, hence low VTH improves speed.

Example: Increased Fall Time Due to Manufacturing
Error
' 1
Ron1 || Ron1  2 RON 1
  W   W  '  
nCox         VDD  VTH 1  
  L 1  L 1  
  
Since pull-down resistance is doubled, the fall time is also doubled.

Power Dissipation of the CMOS Inverter
1 2
PDissipation _ PMOS  C LVDD f in
2
2
Psupply  CLVDD f in
1 2
PDissipation _ NMOS  C LVDD f in
2

Example: Energy Calculation
1 2
Estored  CLVDD
2
1 2
Edissipated  CLVDD
2
2
Edrawn  CLVDD
Power Delay Product
fin CL2VDD
2  2 VTH 1  VTH 1  
PDP    ln  3  4 
 
W V  V  VDD  
nCox   VDD  VTH 1   DD TH 1
 L 1
Ron1=Ron2

Example: PDP
4 1
Ron 
3 W 
nCox   VDD
L 
7.25WL2Cox finVDD
2
PDP 
n
Crowbar Current
 When Vin is between VTH1 and VDD-|VTH2|, both M1 and M2 are on

and there will be a current flowing from supply to ground.

NMOS Section of NOR
 When either A or B is high or if both A and B are high, the

output will be low. Transistors operate as pull-down devices.

Example: Poor NOR
 The above circuit fails to act as a NOR because when A is high

and B is low, both M4 and M1 are on and produces an ill-defined
low.

PMOS Section of NOR
 When both A and B are low, the output is high. Transistors

operate as pull-up devices.

CMOS NOR
 Combing the NMOS and PMOS NOR sections, we have the

CMOS NOR.

Example: Three-Input NOR
Vout   A  B  C 
'
Equal Rise & Fall (µn≈2µp)
W1=W2=W3=W
W4=W5=W6=6W
Drawback of CMOS NOR
 Due to low PMOS mobility, series combination of M3 and M4

suffers from a high resistance, producing a long delay.
 The widths of the PMOS transistors can be increased to counter
the high resistance, however this would load the preceding
stage and the overall delay of the system may not improve.

NMOS NAND Section
 When both A and B are high, the output is low.

PMOS NOR Section
 When either A or B is low or if both A and B are low, the output

is high.

CMOS NAND
 Just like the CMOS NOR, the CMOS NAND can be implemented
by combining its respective NMOS and PMOS sections,
however it has better performance because its PMOS
transistors are not in series.
Example: Three-Input NAND
Vout   ABC 
'
Equal Rise & Fall (µn≈2µp)
W1=W2=W3=3W
W4=W5=W6=2W
NMOS and PMOS Duality
C is in “series” with the

“parallel” combination of A and B
C is in “parallel” with the

“series” combination of A and B
 In the CMOS philosophy, the PMOS section can be obtained from

the NMOS section by converting series combinations to the
parallel combinations and vice versa.

CH 13 Power Amplifier Output Stages and Classes

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CH 13 Power Amplifier Output Stages and Classes

Uploaded by

Copyright:

Available Formats

Chapter 13 Output Stages and Power Amplifiers

 13.1 General Considerations

 Drive a load with high power.

 Cell phone needs 1W of power at the antenna.

 Audio system needs tens to hundreds Watts of power.

 Ordinary Voltage/Current amplifiers are not equipped for

CH 13 Output Stages and Power Amplifiers 2

CH 13 Output Stages and Power Amplifiers 3

 Experiences small load resistance.

 Delivers large current levels.

 Requires large voltage swings.

 Draws a large amount of power from supply.

 Dissipates a large amount of power, therefore gets “hot”.

CH 13 Output Stages and Power Amplifiers 4

CH 13 Output Stages and Power Amplifiers 5

 As Vin increases Vout also follows and Q1 provides more current.

CH 13 Output Stages and Power Amplifiers 6

 However as Vin decreases, Vout also decreases, shutting off Q1

CH 13 Output Stages and Power Amplifiers 8

 As Vin decreases the output waveform will be clipped,

CH 13 Output Stages and Power Amplifiers 9

 As Vin increases, Q1 is on and pushes a current into RL.

Vout=Vin-VBE1 for large +Vin

CH 13 Output Stages and Power Amplifiers 11

 The push-pull stage exhibits a gain that tends to unity when

CH 13 Output Stages and Power Amplifiers 14

 With a battery of VB inserted between the bases of Q1 and Q2,

CH 13 Output Stages and Power Amplifiers 15

 Since VB=VBE1+|VBE2|, a natural choice would be two diodes in

If Vout=0 & β1=β2>>1

CH 13 Output Stages and Power Amplifiers 17

If I1=I2 & IB1≈IB2

CH 13 Output Stages and Power Amplifiers 18

 A CE stage (Q4) is added to provide voltage gain from the input to

 Assuming 2rD is small and (gm1+gm2)RL is much greater than 1,

 If β is low, the second term of the output resistance will rise,

 195 µA of base current in Q1 can only support 19.5 mA of collector

CH 13 Output Stages and Power Amplifiers 24

CH 13 Output Stages and Power Amplifiers 25

 I1 is added to the base of Q2 to provide an additional bias current

Min Vin≈0 Min Vin≈VBE2

 Using negative feedback, linearity is improved, providing

Pav ,max  T1VCC

 Maximum power dissipated across Q1 occurs in the absence of

Avg Power Dissipated in I1

CH 13 Output Stages and Power Amplifiers 32

 Maximum power occurs between Vp=0 and 4Vcc/π.

CH 13 Output Stages and Power Amplifiers 35

 Using diode biasing prevents thermal runaway since the

Emitter Follower Push-Pull Stage

 Efficiency is defined as the average power delivered to the load

Emitter Follower Push-Pull

Class A: High linearity, low efficiency

Class B: High efficiency, low linearity

Class AB: Compromise between

CH 13 Output Stages and Power Amplifiers 39

 14.1 General Considerations

 In order to eliminate the unwanted interference that

Given: Adjacent channel Interference is 25 dB above the signal

Design goal: Signal to Interference ratio of 15 dB

Solution: A filter with stop band of 40 dB

Given: Adjacent channel Interference is 40 dB above the signal