REVIEW OF MOSFET CAPACITANCES

The capacitances usually given in fF/µm (fF per µm width)

width
THIN OXIDE CAPACITANCE

Cg is the thin oxide capacitance and the two plates are

defined by the gate and the channel areas. The value of Cg
is given by per µm of width :
C =C *L=( /t )*L CG is total thin oxide
g ox ox ox
capacitance
this is per area
Gate capacitance has actually three components:
Gate to source capacitance CGS
Gate to drain capacitance CGD
Gate to bulk capacitance CGB
These components vary based on whether the device is
in cutoff, linear, saturation or in accumulation.
JUNCTION CAPACITANCE

junction capacitance junction capacitance

Junction capacitances are calculated using layout

information.

This capacitance is at the output of an inverter or logic

gate
OVERLAP AND FRINGING CAPACITANCE

This capacitance is
seen from both the
input and the output of
an inverter

There are also overlap capacitances Col on both ends of the

poly gate. They are called gate the drain and gate to source
overlap capacitances.
OVERLAP AND FRINGING CAPACITANCE

The overlap capacitances Col has two components.

components First
component is due to lateral diffusion Cov (under the gate) and
second one is the fringing components. Fringing capacitance
Cf due to gate sidewall and the surface of the drain and the
source
Col=Cov + Cf
INVERTER CAPACITANCES
INVERTER CAPACITANCES

CALCULATION OF CFANOUT
This is the load capacitance component due to the inputs
of subsequent gates.

The value depends on the number of gates.

CALCULATION OF CFANOUT

At each gate input, we have the oxide capacitance

plus two overlap capacitances.
CALCULATION OF CFANOUT

C fanout   CG
CG  CGN  2Co L p  CGP  2Co Ln
CG  Cox LW p  2ColW p  Cox LWn  2ColWn
CG  [Cox L  2Col ][Wn  W p ]
CALCULATION OF CFANOUT

C fanout   CG
CG  [Cox L  2Col ][Wn  W p ]

C G  C g (Wn  W p )

where C g  C ox L  2C ol
For 0.13 μm process, the value of
C ox L  1.6 x10 6 F / cm 2 * 0.1m
 1.6 fF / m
Overlap capacitance is 0.25 fF/μm
C g  C ox L  2C ol  1.6  2(0.25)  2 fF / m

Total capacitance due to thin oxide and overlap is 2 fF/μm

Total INPUT capacitance for an inverter
C G  C g (W )  2 fF / m(Wn  W p )

The Cg is constant at 2 fF/μm for many years!

CALCULATION OF INVERTER SELF CAPACITANCE CSELF

CSELF is the sum of the capacitances connected to the output.

we only look at capacitors connected to drain.

CALCULATION OF INVERTER SELF CAPACITANCE CSELF
Miller Effect in Overlap capacitance calculation for CSELF

As inverter switches, at the

input we have 0 to VDD, and
at the output VDD to 0
transition.
Since overlap capacitance
experiences 2VDD voltage
swing. Then we take 2 times
the overlap capacitance for
each transistor.
This is called Miller effect
modeling.
Cself  CDBn  CDBp  2Co L p  2Co Ln
Cself  C JnWn  CJpWp  2Col (Wn  Wp )
For simplification and convenience, in-hand calculation
C eff is defined and includes the effect of both overlap
and junction capacitances.

Cself  C JnWn  C JpW p  2Col (Wn  W p )

Ceff  C J  2Col
Cself  Ceff (Wn  W p )

For 0.13μm technology, average junction capacitance

approx 0.5 fF/μm and overlap capacitance is 0.25fF/μm.

Ceff  C J  2Col  0.5  2(0.25)  1 fF/ m

CMOS INVERTER CONCEPTS
CMOS INVERTER CONCEPTS
CALCULATION OF INVERTER SWITCHING THRESHOLD
The inverter threshold is defined as VSP=Vin=Vout.

For Vin=Vout, both transistors are expected to be in saturation

mode.
Since CMOS inverter exhibits large noise margins and a very
sharp voltage transfer curve transition and the inverter
threshold is an important parameter of DC performance.
performance
VSP
where, n = µn.Cox.Wn/Ln and p = µp.Cox.Wp/Lp

VSP switching point voltage is then found as:

PROBLEM

Find n and p such that the switching point voltage of a

CMOS inverter is 2.5 V. Assume VDD=5 V

We find that n=p assuming same threshold voltages (VTN=|

VTP|) 1

n = p = µnCox Wn/Ln = µpCox Wp/Lp

 n = p = µnCox Wn/Ln = µpCox Wp/Lp

We assume that gate oxide thickness tox,

hence Cox is same for both transistors.

µn (Wn/Ln)= µp( Wp/Lp)

Wp /L p µ n 580 cm 2 /V.s
  2
 2.5
Wn /L n µ p 230 cm /V.s
 Wp /L p
 2.5
Wn /L n

Since channel length is same Ln=Lp for a given

technology, this implies that

Wp =2.5 Wn
Usually the width of PMOS is taken 3 times the width
of a NMOS (but sometimes 2).
This allows equal rise and fall times at the output for
a square wave signal at the inverter input.
Increasing ratios cause inverter switching point to
move to left.
n = µnCox Wn/Ln p = µpCox Wp/Lp

Sizing of a CMOS Inverter

The ON resistance of a PMOS and NMOS is not constant. It
is a nonlinear function of the voltage across transistor.
However an average value can be calculated by integration
over a region of interest (See more on Rabaey’s book).

The equivalent resistance values usually given in a tabular

form for a given VDD voltage. These average values are
obtained using simulation for W/L=1
For VDD=2.5 Volts in 0.25 micron technology:
Reqn=12.5 kOhm/square (W/L=1)
Reqp=30 kOhm/square (W/L=1)
Total NMOS turn on resistance: RN=Reqn(L/W)n
Total PMOS turn on resistance: RP=Reqp(L/W)P
We have just seen that for VDD=2.5 Volts in 0.25
micron technology:
Reqn=12.5 kOhm/square (W/L=1)
Reqp=30 kOhm/square (W/L=1)

The effect of different electron and hole mobility values

are reflected in this numbers.
Inverter Delay Calculation
We will calculate 50% delay (propagation delay) between
the input and the output.

Mainly, tPHL and tPLH

Inverter Delay Calculation

We assume input changes from VOH (high) to VOL (low),

NMOS transistor (pulldown) transistor is OFF, while
PMOS transistor (pullup) is ON

VOH

VOL
 input while
goes output We will calculate 50% delay.
low rises
This corresponds to the
voltage level VDD/2 on the
capacitor.
NMOS
cutoff

when input goes from VOL

to VOH , NMOS is ON and
VOH
discharges the capacitor.
Lumped load capacitance
VOL
discharges thru the
pulldown device.
 we could also use RC charging and
discharging behavior to calculate
input low
delays:
NMOS
cutoff
vo  VDD (1  e  t / RPCL )

to find 50% delay, we replace vo  VDD / 2

t PLH  0.69 RP C L

Total PMOS turn on resistance: RP=Reqp(L/W)P

The capacitor is dischargin g, and then
vo  VDD e t / RN CL
VDD
to find 50% delay, we replace vo 
2
t PHL  0.69 RN C L

Total NMOS turn on resistance: RN=Reqn(L/W)n

We’d like to have equal rise time and fall time (tPLH=tPHL),

t PHL  0.69 RN C L t PLH  0.69 RP C L

this requires RN=RP

Since RN=RP=Reqn(L/W)n=Reqp(L/W)P

Assume, Reqn=12.5 kOhm/ Reqp=30 kOhm/

Finally (W/L)P3*(W/L)N or WP=3WN

We have just formulated inverter propagation delay:

t PHL  0.69 RN C L t PLH  0.69 RP C L

Here,

Lumped load capacitance CL includes the output

capacitance of the inverter, the input capacitance of the

following gate(s) and any interconnect capacitance
between the inverter and gate(s).
This is expressed as

CL = Cself+Cwire+Cfanout

where

Cself (Cout) the output capacitance of the inverter

Cfanout (CL) the input capacitance of the following gate(s)

Cwire= the wire capacitance

Here, we assume wire is short enough to be
taken as one simple capacitor (lumped C).
To derive this circuitry for load capacitance calculation, we
need to know how to calculate inverter capacitances

Fanout capacitance is the summation of input

capacitances of gates that are serving as load to the
interconnect line
input low

NMOS
cutoff
Energy taken from the supply during signal
transition:
Energy taken from the supply
Energy dissipated in PMOS
We got f cycles in a second: