Factors that impact the critical charge of memory elements
Tino Heijmen
Philips Research Laboratories (WAY41), High Tech Campus 5, 5656 AE Eindhoven,
The Netherlands, email: tino.heijmen@philips.com
Damien Giot and Philippe Roche
ST Microelectronics, Central CAD & Design Solutions, 850 Rue Jean Monnet, 38926 Crolles Cedex,
France, e-mail: {damien.giot,philippe.roche}@st.com
Abstract
In the current paper we investigate the factors that affect
the critical charge (Qcrit) for a soft error in a memory cell.
Also the spread of Qcrit due to variations in the transistor
model parameters is studied. The role of the current
waveform that is applied in the simulation, the current
pulse width, and the inclusion of back-end parasitics are
discussed. Furthermore, we treat the impact on Qcrit of
supply voltage, temperature, and process variant. Also,
the paper deals with the effects of parameter variations
through the node capacitance and the PMOS ON-current.
Finally, we show the importance of the spread in Qcrit and
demonstrate that detailed knowledge about the current-
pulse width is necessary for accurate SER estimation.
1. Introduction
Radiation-induced soft-errors are an increasingly
important reliability issue in deep-submicron CMOS
integrated circuit (IC) design [1]. On the one hand, the
number of sensitive nodes tends to grow with every new
product generation. On the other hand, the soft-error rate
(SER) per data bit stays roughly constant (RAM) or
increases (logic) [1],[2]. As a consequence, advanced
characterization and mitigation methods are required in
order to assure IC reliability.
Soft errors are caused by two types of radiation: (1)
alpha particles emitted by radioactive impurities in IC and
package materials and (2) high-energy neutrons resulting
from the interaction of cosmic radiation with the earth’s
atmosphere [1]. When an alpha particle hits silicon it
generates charges in the form of electron-hole pairs. A
neutron does not ionize the material directly, but interacts
with atoms via elastic or inelastic collisions or via nuclear
fission. The resulting products are capable of inducing
electron-hole pairs.
Drift and diffusion can transport the generated charges
to circuit nodes. This causes a current pulse that disturbs
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the node level and may lead to a corrupted data bit, called
a soft error. In a memory cell, such as an SRAM cell or a
flip-flop, a soft error means that the state of the cell has
changed (‘bit flip’). An important measure for the soft-
error-sensitivity of a circuit node is the critical charge
(Qcrit), which is the minimum amount of charge that needs
to be injected in a circuit node to produce a soft error.
Qcrit can be calculated efficiently using a circuit
simulator. In the present work, we report results from
circuit simulation demonstrating the impact of various
factors on the critical charge. Because Qcrit is directly
related to the soft-error rate, understanding of the effect of
these factors is important to estimate the SER of a circuit.
First, the impact of the current waveform and of several
external factors is discussed. Then, the effect of individual
parameter variations and the Qcrit distribution are treated.
2. Simulation methodology
Critical charge definition
Many methods have been reported in the literature for
the calculation of the critical charge. In the current work,
we compute Qcrit by circuit simulation using a current
source to model the charge collection. For a given
waveform of the current pulse, the amplitude of the pulse
is varied in order to find the critical value for which the
pulse causes an upset. Qcrit is then defined as the total
amount of charge contained by this critical current pulse.
An SRAM cell that is hit by an ionizing particle is
schematically depicted in Figure 1. The dashed
rectangular shows the drain diffusion area of the pull-
down NMOS transistor N1, the area that is most sensitive
in the case that the cell stores a logical 1, i.e., node INT1
is high and node INT2 is low. The current source Jelec
represents the current pulse due to charge collection. The
subscript “elec” denotes that electrons are being collected,
which results in a lowering of the node level of INT1. As
a model vehicle a 90-nm SRAM cell is used.
 Figure 1: Schematic of an SRAM cell.

Current-pulse characteristics Figure 2: Waveform models for current pulses

Different waveforms can be used for the current pulse
in the critical charge calculations. A commonly used
waveform is the expression reported by Freeman, using a
single timing parameter W [3],
Freeman 2 Q tot t § t ·
I pulse (t) exp¨ ¸ .
S IJ IJ © IJ ¹
An alternative is to use a double-exponential
waveform with a rise time (Wr) and fall time (Wf) parameter,
dbl -exp Qtot ª § t · § t ·º
I pulse (t) «exp¨¨  ¸¸  exp¨¨  ¸¸» . (2)
IJ f  IJ r «¬ © IJ f ¹ © IJ r ¹»¼
Especially for the collection of charges induced by a
neutron the diffusion model is relevant, characterized by
Imax and tmax, where tmax is the time at which the maximum
current Imax is observed [4],
3
diff § t · 2 § 3t ·
I pulse I max ¨ e max ¸ exp¨  max ¸ .
(t) (3)
© t ¹ © 2t ¹
Examples of the three different waveforms are
depicted in Figure 2. The parameters where chosen such
that the total charge contained by the current pulse equals
10 fC and the full width at half maximum (FWHM) was
equal to 161.5 ps in all three cases. While the Freeman
expression of Eq. (1) and the double-exponential model of
Eq. (2) result in a similar waveform, if the proper time
constants are chosen, the diffusion model gives a current
pulse with a relatively long offset time and a long ‘tail’.
The different waveforms result in different values of Qcrit
for our model vehicle, ranging from 3.87 to 7.26 fC, as is
shown in Table 1.
Not only the waveform of the current pulse, but also
the pulse width has a strong effect on the resulting Qcrit, as
is shown in Figure 3, where the critical charge is given for
a double-exponential waveform with a fixed rise time
constant Wr=0.1 ps and a varying fall time constant Wf. The
FWHM is in this case almost a linear function of Wf: wpulse
induced by ionizing particles.
Model Timing parameters (ps) Qcrit (fC)
Freeman W=90 3.87
Double-exp. Wr=16.1, Wf=161 4.39
(1) Double-exp. Wr=33, Wf=161 4.55
Double-exp. Wr=0.1, Wf=232 5.26
Diffusion tmax=59.8 7.26
Table 1: Qcrit of a 90-nm SRAM cell for different
waveforms; all pulses have a FWHM of 161.5 ps.
| 0.7 Wf. For large values of Wf Qcrit is an almost affine
function of Wf and consequently of the pulse width.
Table 1 and Figure 3 show that it is important to
clearly define the waveform that is applied, including the
timing parameters. Device simulations reported in the
literature have shown that the width of the waveform can
vary from a few picoseconds to hundreds of picoseconds
(see the paper by Walstra and Dai in [1], pp. 358364).
Obviously, a narrow current pulse represents the worst-
case situation, because Qcrit is minimal. A narrow current
pulse corresponds to an event in which the track of an
ionizing particle intersects the drain of an NMOS or
PMOS transistor in the OFF-state. However, theoretical
studies showed that typically 80-90% of the neutron-
induced SER is represented by events in which the track
does not intersect the drain [5]. In these cases diffusion is
the main collection mechanism and the current pulses are
relatively wide. This result demonstrates that both narrow
and wide current pulses have to be considered in Qcrit
simulation. In the remainder of the paper we consider
double-exponential waveforms for the current pulse, with
Wr=0.1 ps and Wf=1 or 90 ps. These two cases are
representative for a drain-intersecting and a non-drain-
intersecting hit, respectively.

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Figure 3: Dependency of Qcrit on pulse width
Back-end parasitics
Including back-end (BE) parasitic capacitances in the
critical charge simulation affects the results, as it does for
performance and for power dissipation. For our 90-nm
SRAM cell Qgate (i.e., the sum of charges on the transistor
gates that are connected to a storage node) equals 0.33 fC.
In contrast, the sum of charges on the parasitic
capacitances equals 1.06 fC at 1.2 V, which is more than
3u as large. This difference is reflected in Figure 3, where
Qcrit as a function of Wf is compared for the SRAM cell
with and without parasitic capacitances. Including
parasitics increases Qcrit with about 1 fC. This difference
is roughly independent of Wf, because the stabilization by
the pull-up PMOS transistor (discussed below) is not
affected by the parasitics. Unless indicated otherwise, all
results presented in this paper have been obtained with
BE parasitics included.
Approximations to Qcrit
A well-known and often used approximation to the
critical charge is the nodal charge,
Qcrit | Qnode C node VDD . (4)
The expression in Eq. (4) ignores the contribution from
the PMOS transistors in the dynamic stabilization of the
node charge during the upset. This leads to an
underestimation of Qcrit, especially if the current pulse is
relatively wide. For example, the node charge of our 90-
nm SRAM cell at 1.2 V is 1.39 fC if BE parasitics are
included. Comparison with Figure 3 shows that even for a
narrow pulse (Wf=1 ps) Qcrit is 33% higher than Qnode. For
wider current pulses the difference is much larger.
A more accurate approximation is to add to Qnode a
term representing the stabilization current from the pull-
up transistors. This term is usually defined as the product
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of the ON-current of the stabilizing PMOS transistors
times the pulse duration [6],
Qcrit | Qnode  I P,ON wpulse C node VDD  I P,ON wpulse . (5)
However, the current supplied by the PMOS transistor
is not constant during the upset. Also, the definition of the
pulse width wpulse affects the result. Furthermore, Eq. (5)
neglects the contribution from the pull-down NMOS
transistors to the cell stabilization. Still, Eq. (5) is much
more accurate than Eq. (4) and is useful to qualitatively
explain changes in Qcrit. For the PMOS transistors in our
SRAM cell the maximum ON-current is 15 PA. If the
FWHM equals 161.5 ps, the resulting Qcrit according to
Eq. (5) is 3.81 fC. If we compare this value with the data
in Table 1, we see that the approximation still
underestimates the simulated results, but the difference is
much smaller. Especially the agreement with the
simulation using the Freeman waveform is very good.
3. External factors affecting Qcrit
For a given circuit netlist and a fixed waveform for the
current pulse, the results of the Qcrit simulation depend on
several factors. A very important factor is the supply
voltage VDD. A higher value of VDD implies that a larger
amount of charge represents one bit and, consequently,
more effort is required to upset the bit. Figure 4 shows the
voltage-dependency of Qcrit for the 90-nm SRAM cell for
two double-exponential waveforms: one with Wf=1 ps and
one with Wf=90 ps (Wr=0.1 ps in both cases). For both pulse
widths Qcrit is an affine function of VDD. The voltage
dependency is much stronger for the wider current pulse,
because the drive strength of the pull-up transistors is
strongly affected by VDD. At low VDD, the circuit needs
more time to either flip or return to its initial state.
With technology scaling the number of process
variations within a given technology node is increasing.
The 90-nm CMOS technology of the Crolles2 Alliance
consists of a LP (low-power) and a GP (general-purpose)
process variant. The Qcrit of the 90-nm SRAM cell was
calculated for both the LP and GP processes. The results,
presented in Figure 4, show that Qcrit for the two processes
is almost identical at Wf=1 ps but is 30-40% larger for GP
at Wf=90 ps. This demonstrates that Qnode is similar in both
processes; but that the higher drive strength of the
transistors in the GP process significantly stabilizes the
node charges. In practice this effect is largely
compensated by the fact that the supply voltage of GP
applications is usually lower than for LP: the nominal VDD
for GP and LP is 1.0 and 1.2 V, respectively.
Temperature does not significantly affect the critical
charge. Both for narrow and for wide current pulses Qcrit
varies with less than 3% over the range T = 40 to 125 oC.
This is confirmed by experimental SER results, which do
not show a significant dependency on temperature.
 Figure 4: Dependency of Qcrit on VDD Figure 5: Technology scaling of Qcrit at nominal VDD.
The error bars show the spread due to process
Technology scaling has caused an ongoing decrease in
variations, cf. Sec. 4.
Qcrit. Figure 5 shows that the critical charge at nominal
VDD is approximately divided by a factor of 2 at every
technology migration, both for wide and narrow current
pulses. However, because the SER per bit also depends on
the charge collection efficiency, the Qcrit reduction has not
lead to an exponential increase in SER [1],[7],[8].

4. Factors affecting the spread in Qcrit

Recent studies demonstrated that controlled variations
of the layout [9] and of the threshold voltage [10] affect
the SER and can be used to increase the robustness of
circuits. As discussed in the previous section, processing
variants (GP, LP) affect Qcrit and consequently the
sensitivities of circuits to ionizing particles. Furthermore,
a strong dependency of the critical charge to (unwanted)
process variations has been reported for SRAMs [7],[8].
Process variations affect both the physical transistor Figure 6: Variation in Qcrit for transistor model
parameters (e.g., width, length, oxide thickness) and the
parameters set at their extreme values (4V, +4V).
electrical parameters (e.g., threshold voltage, junction
capacitance). A study of the impact on Qcrit of variations
in the process parameters is mandatory to determine the computed for each value of the transistor model
sensitivity range of current and future IC technologies parameter. The Qcrit simulations were repeated for various
radiation under terrestrial conditions. pulse durations (Wf). Results are shown in Figure 6.
Parameter variations affect Qcrit both through the node
Individual parameter variations charge Cnode and the PMOS current IP,ON, cf. Eq. (5). Cnode
can be expressed as a function of L, W, and Cj as follows,
Simulation results show that variations in the transistor İ
C node C gate  C j  C par WL ox  C j  C par , (6)
width (W), the transistor length (L), the threshold voltage t ox
of the PMOS transistor (VT,P < 0), and the junction
where Cpar denotes the sum of BE parasitic capacitances.
capacitance (Cj) have the most significant effect on Qcrit.
The stabilizing PMOS transistor is in its linear operational
The simulations were based on the SRAM schematic
region with VGS | VDD and VDS | 0. The magnitude of its
presented in Figure 1 with GP transistor models. A
ON-current, as a function of W, L, and VT,P, then equals
double-exponential current pulse was used with Wr=0.1 ps
μİ W
and Wf varying from 1 to 90 ps. Each parameter was I P,ON VGS  VT,P VDS . (7)
successively set to its extreme values (4ı, +4ı). Qcrit was t ox L

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 Table 2 summarizes the effect on Cnode and IP,ON of
positively-signed variations in the transistor model
parameters, according to Eqs. (6) and (7).
Parameter W L VT,P Cj
Effect on Cnode + + 0 +
Effect on IP,ON +  + 0
Table 2: Effect of (positive) parameter variations.
Figure 6 shows that W is the parameter with the
largest influence on Qcrit at moderate pulse widths. For a 1
ps pulse a +4V variation in W results in a 6% increase in
Qcrit. For a wider pulse, W +4V variation induces an even
higher Qcrit increase (+10% at 90 ps). As is shown by Eq.
(5), if the pulse duration (Wf) increases, the Qcrit value is
more and more driven by its IP,ON wpulse component. When
W increases, transistors have higher drive currents (e.g.,
IP,ON) and higher nodal capacitances. Qcrit varies almost
linearly with W, in accordance with Eqs. (6) and (7).
Also the transistor length L significantly affects Qcrit,
especially for large pulse widths. A +4V variation in L
increases Qcrit for pulses with Wf below 20 ps (+3% for Wf =
1 ps), but causes a decrease for wider pulses (5% for Wf =
90 ps). This is because a larger L implies a larger Cnode but
a smaller IP,ON. The latter has a dominant impact for large
pulse widths. Note that the Qcrit variation is larger for the
4V variation in L than for the 4V variation, because of
the 1/L dependency of IP,ON, cf. Eq. (7).
Figure 6 also presents the Qcrit variation as a function
of the PMOS threshold voltage (VT,P). VT,P variations have
a negligible influence on Qcrit for a 1 ps pulse duration. A
progressive increase of the pulse width induces an
increase of Qcrit for a +4V variation of VT,P. This is
because when VT,P is increased (i.e., becomes less
negative), IP,ON is increased. If VT,P is decreased, Qcrit is
decreased for wide pulses. This symmetric behavior of the
+4V and 4V curves is explained by the slope of IDS(VGS)
curve which is quasi-constant over the threshold voltage
variation range (VT,P 4ı, VT,P +4ı).
The NMOS threshold voltage VT,N (not shown in
Figure 6) does not have a large influence on Qcrit for both
narrow and wide pulses. The variation in VT,N is more
important for a particle’s strike on the OFF-state PMOS.
However, it is not under the scope of this paper, which is
focused on upsets due to a particle strike at the drain of an
NMOS in the OFF-state, which represents the worst case.
Qcrit has a well-defined behavior as a function of the
junction capacitance Cj: they increase or decrease
together. Qcrit variations are larger for short pulses
(±4.5%) than for longer ones (±2%). This cannot be due
to the current provided by the PMOS transistor (IP,ON)
since Cj does not affect it. This decrease can be explained
by a higher IP,ON wpulse participation in the Qcrit value for
90 ps (60%) than for 1 ps (2%) pulse duration.
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Statistical distribution of Qcrit
The statistical distributions of Qcrit of our 90-nm
SRAM cell have been calculated for five different process
corners of the LP process: fast-N, fast-P (FNFP); fast-N,
slow-P (FNSP); nominal (NOM); slow-N, fast-P (SNFP);
and slow-N, slow-P (SNSP). The simulation details can
be found elsewhere [7],[8]. Figure 7 shows the results for
a narrow current pulse (Wr=0.1 ps, Wf=1 ps). The spread in
Qcrit is the same for the five process corners. The curves
for the FNFP, NOM, and SNSP corners almost overlap.
Qcrit for FNSP corner is a slightly smaller, while the SNFP
corner gives a somewhat larger Qcrit. A fast transistor
means a relatively large W and a relatively small L. For a
PMOS transistor this results in a stronger drive and,
consequently, a better stabilization of the node charge. An
NMOS transistor affects Qcrit through gate and junction
capacitances. Effectively, a faster NMOS results in a
lower node charge. As a consequence, Qcrit is the largest
for the SNFP corner and the lowest for the FNSP corner.
Figure 7: Qcrit distributions for Wf = 1 ps.
These calculations were repeated for a wide current
pulse (Wf=90 ps). The results are shown in Figure 8. The
SNSP corner clearly gives the smallest Qcrit and the FNFP
corner clearly the largest. The FNSP data are between the
SNSP and NOM results, while the SNFP curve is between
the NOM and FNFP data. For such a large pulse width,
the stabilization of the node charge by the pull-up and
pull-down transistors plays a dominant role. Variations in
Cnode are less important. A faster PMOS transistor results
in better node-charge stabilization. The pull-down
(NMOS) has a smaller stabilizing effect. Therefore, a
slow NMOS transistor only partly compensates the
impact of fast PMOS transistor [2]. Similarly, a fast
NMOS transistor partly counterbalances a slow PMOS
transistor.
The results show that wide current pulses lead to large
variation in Qcrit, while the spread for narrow pulses is
relatively small. Therefore, detailed information about the
 distribution of pulse widths is necessary to determine the
spread in SER for a given technology.
Figure 8: Qcrit distributions for Wf = 90 ps.
The error bars in Figure 5 show the spread in Qcrit due
to process variations for 180-, 130-, and 90-nm SRAMs.
The spread is defined by the 3V value of the best-case
process corner and the 3V value of the worst-case
corner. The relative spread at Wf=90 ps is comparable for
the three technologies. At Wf=1 ps the spread is much
smaller and decreasing with technology scaling. The ratio
of the largest Qcrit at Wf=90 ps and the smallest Qcrit at
Wf=1 ps equals 2.7, 2.4 and 2.6 for 180-, 130- and 90-nm
technology nodes, respectively.
5. Conclusions
Essential in Qcrit simulations is the model for the
current pulse that is induced by an incident particle. Both
the waveform and the width of the pulse significantly
influence the simulation result. Including back-end
parasitics in the simulation adds a constant term to Qcrit
(|1 fC for a 90-nm SRAM cell). The critical charge is an
affine function of VDD but is independent of temperature.
For large pulse widths Qcrit differs for different process
variants, due to variations in the transistor current.
Results on the Qcrit sensitivity to variations in the
individual transistor parameters show that Eq. (5) is
useful to get qualitative results and evolutions. They also
demonstrate that the Qcrit sensitivity to variations in
physical and electrical parameters depends strongly on the
duration of the applied current pulse. For narrow pulses
(Wf  20 ps) Qcrit is mainly affected by variations in the
CnodeVDD term. The transistor width (W) and length (L)
and the junction capacitance (Cj) then influence Qcrit
through the node capacitance. For wide pulses (Wf ! 20 ps)
the IP,ON wpulse component is increasingly dominating the
Qcrit variation. The parameters W and L and the PMOS
threshold voltage (VT,P) influence Qcrit through IP,ON .
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For small pulse widths the spread in Qcrit is relatively
small and the dependency on the process corner is weak
(Figure 7). However, for wide current pulses the spread is
much larger and there is a clear correlation with the
process corner (Figure 8). The strong dependency on the
width of the current pulse demonstrates that accurate
knowledge about the pulse-width distribution is necessary
to accurately calculate the spread in SER. Device-level
simulations will have to be performed to obtain this
current-pulse information. Simulations on SRAMs in
180-, 130-, and 90-nm technologies show a comparable
spread in the Qcrit distribution, measured from the 3V
value of the slowest process corner to the +3V value of
the fastest corner. The average Qcrit value decreases with
roughly a factor of 2 with every technology generation.
Acknowledgements
The authors would like to thank Gilles Gasiot and
Keith Forbes for many insightful discussions and Bram
Kruseman and Thomas Mérelle for reviewing the paper.
References
[1] J. Maiz and N. Seifert (Guest Eds.), “Special issue on soft
errors and data integrity in terrestrial computer systems”,
Trans. Dev. Mater. Reliability, vol. 5, no. 3, Sep. 2005.
[2] T. Heijmen et al., “A comparative study on the soft-error
rate of flip-flops from 90-nm production libraries”, Proc.
Int’l Reliability Physics Symp. (IRPS), 2006, pp. 204211.
[3] L.B. Freeman, “Critical charge calculations for a bipolar
SRAM array”, IBM J. Res. Dev., vol. 40, no. 1, Jan. 1996,
pp. 7789.
[4] T. Mérelle et al., “Criterion for SEU occurrence in SRAM
deduced from circuit and device simulations in case of
neutron-induced SER”, Trans. Nucl. Sci., vol. 52, no. 4,
Aug. 2005, pp. 11481155.
[5] G. Hubert et al. “A review of DASIE code family:
contribution to SEU/MBU understanding”, Proc. Int’l On-
Line Test Symp. (IOLTS), 2005, pp. 8794.
[6] P. Roche et al., “Determination of key parameters for SEU
occurrence using 3-D full cell SRAM simulations”, Trans.
Nucl. Sci., vol. 46, no. 6, Dec. 1999, pp. 13541362.
[7] T. Heijmen and B. Kruseman, “Impact of process
variations on the alpha–particle-induced SER of embedded
SRAMs”, Proc. Int’l Conf. Memory Technology and
Design (ICMTD), 2005, pp. 7780.
[8] T. Heijmen and B. Kruseman, “Alpha-particle induced
SER of embedded SRAMs affected by variations in
process parameters and by the use of process options”,
Solid-State Electronics¸ vol. 49, pp. 17831790, no. 11,
Nov. 2005.
[9] H. Fukui et al., “Comprehensive study on layout
dependence of soft errors in CMOS latch circuits and its
scaling trend for 65 nm technology node and beyond”,
Proc. Symp. VLSI Technology, 2005, pp. 222 – 223.
[10] V. Degalahal et al., “The effect of threshold voltages on
the soft error rate”, Proc. Int’l Symp. Quality Electronic
Design, 2004, pp. 503 – 508.