Delay Insensitive Logic with Increased Fault Tolerance and
Optimized for Subthreshold Operation
I. Santos and E. MacDonald
The University of Texas at El Paso
Email: emac@utep.edu, Tel: (915) 747-6959
Abstract—Biomedical and space applications require
both reduced power consumption - extending the life
of the battery - as well as reliable operation in harsh
conditions particularly in the context of radiation or
noise sources. A common approach for reducing
power is to lower the supply voltage to the subthreshold
regime (Vdd < Vth). However, subthreshold operation
also results in an increased vulnerability to radiation
and noise as well as an exponential increase in delay
variation of the circuits and associated clock trees,
which may lead to incorrect operation. Asynchronous
logic has shown a natural adaptation to subthreshold
operation due to the replacement of the clock by the
efficient implementation of handshaking signals and
communication protocols – eliminating the sensitivity
to delay variation as well as a further reduction of
power by eliminating the highly active clock. Delay
Insensitive logic mitigates the performance reduction
and delay variation sensitivity of subthreshold circuits
but does not address the reduction in fault tolerance.
Consequently, a fault tolerant scheme applied to
current NULL Convention LogicTM (NCL) gates is
proposed - providing tolerance to Single Event Upset
(SEU) provoked by radioactivity, while operating in the
subthreshold region. Although the values of critical
charge (Qcrit) decrease dramatically for traditional
NCL cells from 189 fC @ 1.5 V to 26 fC @ 0.3 V, the
proposed cells – simulated with MIT Lincoln Lab’s
150 nm XLP CMOS process - were virtually fault
tolerant (Qcrit > 1000 fC) for both supply voltages.
I. DELAY INSENSITIVE LOGIC
Asynchronous circuits with timing assumptions are
called Quasi-Delay Insensitive [1]. Alternatively, a
Delay Insensitive circuits eliminates the need for any
timing assumptions and the logic relies on the effective
execution of dual-rail or quad-rail signals and registers –
all of which implement a handshaking protocol. One of
the most reliable approches for Delay Insensitive
systems is the NULL Convention LogicTM (NCL) [2].
This convention represents a bit with two signals (e.g.,
dd.0, d.1) that characterize one of four possible logic
states (e.g., d.0=0, d.1=0  NULL state; d.0=1, d.1=0
 FALSE state; d.0=0, d.1=1  TRUE state; d.0=1,
d.1=1  illegal state). Furtheremore, NCL logic gates
have a state-holding property that allows the
preservation of the output with TRUE or FALSE data
978-1-4799-1361-9/13/$31.00 ©2013 IEEE
until a NULL state is presented to all inputs, i. e. the
reset condition.
II. SUBTHRESHOLD OPERATION
Operating in a subthreshold regime (Vdd < Vth) leads
to a dramatic reduction in the dynamic power at the
expense of an increase in circuit delay, vulnerability to
noise and increase in Process, Voltage, and
Temperature delay variations, which can cause
significant differences in the arrival time of the clock
signal to different sequential elements in synchronous
sytems [4]. This clock skew can result in hold time
violations, which in turn can result in incorrect
operation. Asynchronous logic eliminates this concern
by eliminating the clock. Finally, as transistors are
operating in the weak inversion mode in subthresold, the
drive currents provided are exponentially decreased and
when unintentional charge is introduced into a node (e.g.
radiation), the reduction in drive strength results in
difficulty in removing the charge in order to recover.
III. FAULT TOLERANCE
Transitor level circuits which include feedback for
maintaining memory have sensitive nodes that are
susceptible to Single Event Upset (SEU). Corruption of
data in an element can be caused by radiation-induced
charge or capacitive-coupled noise. Fault tolerant
circuits require a robust arrangement of transistors that
prevents corruption in the feedback nodes with a backup
slave structure [5-6]. These techniques are crucial for
asynchronous circuits to achieve a robust operation of
dual-rail encoding and handshaking protocols during
periods of irradiation as an upset in the acknowledgment
signal can result in a deadlock.
IV. PROPOSED FAULT TOLERANT SCHEME
For demonstration purposes, a 2-of-3 threshold gate
(TH23) is used to illustrate the concept, which has a
holding-state configuration preserving the ouput when
the inputs are invalid and a reset arrangement as shown
in Fig. 1. The proposed fault tolerant design is based in
dual redundancy with a reduction in transistor count and
an interwoven configuration as shown in Fig. 2. The
upper part of this schematic comprises the original
arrangement of the TH23 optimized to operate in
subthreshold region [3]. The bottom section of the
circuit provides the interlocking redundancy to provide
 Figure 1. Proposed fault tolerant TH23 gate for subthreshold operation.
Figure 1. Traditional TH23 logic gate.

radiation hardness. The inverter of the redundant circuit TABLE I. Simulation results for traditional and proposed TH23
gate.
with output ZR feeds the PFETs of the original circuit
and the NFETs of the redundant circuit. Alternatively, Voltage Qcrit Average Energy Area
the inverter of the original circuit with output Z feeds the TH23
(V) (fC) Delay (ns) (fJ) (um )
PFETs of the redundant circuit and the NFETs of the
Traditional 1.5 189 0.293 763.5 19.8
original circuit. Finally the inverters of both
Proposed 1.5 14535 0.151 1355 50.4
arrangaments are fed by interlaced original and
Traditional 0.3 27 72.7 10.68 27
redundant signals. The interwoven control ensures that
Proposed 0.3 1292 77.2 17.28 50.4
if any one of the data nodes is injected with charge, the
remaining data nodes will provide a data recovery.
order of magnitude is gained in the charge required to
corrupt the cell.
V. SIMULATIONS AND RESULTS
Comprehensive simulations were performed using REFERENCES
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