DESIGN AND PERFORMANCE

ANALYSIS OF THE CMOS INVERTER

 CMOS INVERTER
• We now take a more comprehensive look at
the inverter investigating its performance and
exploring the trade-offs available in its design
CMOS INVERTER- Circuit Structure
CMOS INVERTER- Circuit Structure
• The inverter circuit can be represented by a
pair of switches operated in a complementary
fashion as shown on the previous slide
• Each switch is modeled by a finite on
resistance which is the source-drain resistance
of the respective transistor evaluated near ||
=0
CMOS INVERTER- Circuit Structure
 Static Operation
• When vI  0, vOH  vDD the , output node is
connected to VDDthrough the resistance rof DSPthe

pull-up transistor Q.P

• Similarly, with vI  VDD , vo  VOL , 0the output node is
connected to ground through the resistance ofrDSN
the pull-down transistor . QN
• Thus, in the steady state, no direct-current path
exists between VDD and ground, and the static-current
and the static-power dissipation are both zero
Voltage Transfer Characteristics-VTC
 Static Operation
• The fact that and are independent of device
dimensions makes CMOS very different from
other forms of MOS logic
• The CMOS inverter can be made to switch at
the midpoint of the swing 0 to that is at /2 by
appropriately sizing the transistors
 Static Operation
• Specifically it can be shown that the switching
threshold
VDD  Vtp  kn k p Vtn
Vth  10.8
1  kn k p

• Where kn  k '(W / L)n and k p  k ' p (W / L) p from

which we see that for the typical case where
=||, /2 for =
 Static Operation-(matching)
• Thus a symmetrical transfer characteristics is
obtained when the devices are designed to
have equal transconductance parameters a
condition we refer to as matching
 Example
• For example for a 0.25m process for which
p/n=3, L= 0.25m
(W/L)n=0.375m/0.25 m
(W/L)p=1.125m/0.25 m

• Here Wn=1.5L and Wp=4.5L

 Matching advantage
• Matching the transconductance parameters of
and provides the inverter with equal current
driving capability in both (pull up and pull
down)
• It also makes = thus an inverter with matched
transistors will have equal propagation delays
 Noise Margins
• When the inverter threshold is at /2 the noise
margins and are equalized and their values are
maximized such that
==(+ )
• Since typically =0.1 to 0.2 the noise margins are
approximately 0.4 this value being close to half
the power supply voltage makes the CMOS
inverter nearly ideal from a noise immunity
standpoint
 Exceptions
• Although it has been emphasized that
matching and is desirable there are occasions
in which this scaling is not adopted. One might
for instance forgo the advantages of matching
in return for reducing chip area and simply
make ( )n = ( )p