An Asynchronous Cell Library for Operation in Wide­
Temperature & Ionizing-Radiation Environments
l 2 2 t
John Brady , A. Matthew Francis , Jim Holmes , Jia Di , H. Alan Mantooth
2 3
I Department of Computer Ozark Integrated Circuits
Science and Computer 700 W. Research Blvd.
Engineering Fayetteville, Arkansas 72701
University of Arkansas {francis, holmes}@ozarkic.com
Fayetteville, Arkansas 72701
{jdbrady, jdi}@uark.edu
Abstract - An asynchronous NULL Convention Logic (NCL)
gate library is developed for applications in space environment
with temperatures ranging from -196° C to 125° C with
radiation exposure. To further improve radiation-immunity
and temperature-stability dual high-density metal-insulator­
metal (DMIM) capacitor-based delay elements (based on
DMIM capacitors available in the IBM 9HP process) and an
asynchronous Dual Interlocked Cell (DICE)-based DFF are
introduced. Results from temperature simulation and
radiation analysis are shown.
Table of Contents
1. Introduction . . ..................................................................1
2. Background......................................................................2
3. NCL Gate Development..................................................3
4. Delay Elements................................................................5
5. Asynchronous Storage Devices......................................6
6. Radiation Analysis.......................................................... 8
7. Conclusion........................................................................9
Acknowledgements..............................................................9
References...........................................................................9
Biographies ........................................................................10
1. Introduction
The extreme nature of space application for electronic
systems brings many challenges to chip design, due to
radiation exposure and an extreme temperature range that
may cause soft errors, or even physical damage to a chip.
Because of these challenges, asynchronous design
methodologies, such as NULL Convention Logic (NCL),
may be considered for their advantages in providing
stability in such a harsh environment [1][2].
By using a dual-rail logic system, the data in an NCL circuit
is inherently hardened against radiation-induced SEUs
because two SEUs are required, or a multi-device SEU, to
change a dual-rail logic data's value. In addition, NCL
provides stability in a wide temperature range where a
device's behavior may become erratic due to its delay­
insensitivity. These characteristics of NCL can also be
1
3
Department of Electrical
Engineering
University of Arkansas
Fayetteville, Arkansas 72701
mantooth@uark.edu
leveraged in a redundant system to further provide
mitigation against single-event upsets (SEUs) [3].
This paper is based on research aiming to create an NCL
gate library to be used for designing ICs that operate
reliably in space applications. In addition to the NCL gate
library, new structures have been created for operating in
such an environment, including capacitor-based delay
elements and a DICE-based asynchronous DFF. These cells
are simulated from -196° C to 125° C, and are analyzed
through single-event transient (SET) simulation. Since the
9HP kit models only support temperatures down to -55° C,
90nm models extracted at -196° C are used.
2. Background
NULL Convention Logic (NCL)
NCL is a delay-insensitive asynchronous circuit design
methodology that uses dual-rail logic to create delay
insensitivity. There are three valid states for dual-rail logic
data: DATAO (railo 1 and rail I 0), DATA1 (railo 0 and
= = =
rail'= 1), and NULL (railo =0 and rail' 0) which
=
correspond to Boolean logic 0, 1, and no data [4][5]. The
two rails are mutually exclusive which means that the fourth
state, where railo 1 and rail I 1, is an invalid and unused
= =
state.
NCL circuits are designed with a combination of 27
fundamental gates, which create a complete set of functions.
These gates support up to four single-rail inputs. For most
circuits, a separate function consisting of these fundamental
gates is used to create the value of each rail of a dual-rail
logic signal. Each of the fundamental gates follows the
naming convention THmn (symbol in Figure 1) where m of
the total n inputs are required to be asserted in order to
cause the output value of the gate to be asserted. These gates
use hysteresis meaning once the output is asserted, the
output only becomes deasserted if all inputs are deasserted.
As a result, once a set of gates processes data and
correspondingly gives output data, each of the gates' outputs
has to be deasserted before processing a new set of data to
ensure that the results of two input data are not mixed.

Input 1----1
Input 2 ----1
Outpnt
Inplltn--�
Figure 1: NCL gate symbol [4]
NCL gates may also have reset functionality where the
output can reset to logic 1 or O. If the output of a gate is
asserted after being reset, it is said that the gate resets to
DATA, and if the output of a gate is deasserted after being
reset, it is said that the gate resets to NULL. This is
represented in the naming convention by adding an n, for
NULL, or a d, for DATA, to the name of the gate, such as
TH22d. Resettable gates are used in NCL registers to reset
the circuit to a known state, similar to in a Boolean circuit.
NCL circuits contain two or more sets of delay-insensitive
asynchronous registers in order to create a single or multi­
staged system. These register sets communicate using
handshaking signals called Ko signals. A Ko signal notifies
the previous register set when it is ready for a new DATA or
NULL wave. A DATA wave is a set of data where all dual­
rail values are DATAO or DATAl, and a NULL wave is a
set of data where all dual-rail values are NULL. After
initially resetting a circuit, each register uses completion
logic to determine if a DATA or NULL wave has
completed. If a DATA wave has completed, a request-for­
NULL (rfn) is sent to the previous register by assigning a 0
as the Ko value. Likewise, if a NULL wave has completed, a
request-for-DATA (rfd) is sent to the previous register by
assigning a 1 as the Ko value.
A register consists of three NCL gates: two TH22n gates,
and a THI2b. The TH22n gates provide the reset
functionality and allow the current DATA or NULL wave to
propagate through when requested by the succeeding stage.
The TH12b gate determines when the register is outputting a
DATA value or NULL value and, as a result, requests a
NULL wave or DATA wave. Completion logic, consisting
of TH44 gates, then ensures that all registers in a set are
requesting the same type of wave before changing its
output, the Ko signal. When every register in a set requests a
new DATA or NULL wave, the Ko signal from the set's
completion logic sends an rfd or rfn to the previous stage.
Dual Interlocked Storage Cell (DICE)
A DICE device (Figure 2) creates an SEU-immune latch by
adding two nodes to a normal latch in order to create a four­
node (XO. . . X3 where node X3+1 is node Xo and node XO_I is
node X3) redundancy structure [6]. The set of four nodes
store the data in the latch as two sets of complementary data
(Xo. . . X3 can equal 0101, logic 0, or 1010, logic 1). These
nodes are accessed via transmission gates for read and write
2
operations. The nodes interact such that node X, is controlled
by the pair of nodes on the opposite diagonal, X,-I and X,+I.
This is obtained using complementary feedback through Ni_1
and Pt+l. The inverters in the figure are either P-type
inverters or N-type inverters, as denoted by Nt and Pi' Each
P-type inverter's source is connected to VDD, and each N­
type inverter's drain is connected to GND (these labels in
Figure 2 are omitted for clarity).
DATA_BAR
.-ILJ"
7
ClK
..6...p2
I �----====�-----j
C�K �tK
Figure 2: DICE-based latch [6]
If an N-type transistor is used for the inverter, only an input
value of 1 can turn the inverter on, causing the output to be
O. An input of 0 to this type of inverter turns off the
transistor and does not bring the output to 1. This design
allows for a node, Xi, to only be able to change a node, Xi+l,
to 1 when X, has a value of O. Otherwise, when X, has a
value of 1, the P-type inverter is off and does not change
X,+I or continue to drive Xi+1 to O.
Likewise, only a value of 1 at node X, can cause a change to
node Xi-I, since X, only drives Xi_1 through an N-type
inverter. This configuration causes only two pairs of
inverters to be on at one time. When the cell is in the logic 0
state where the nodes Xo through X3 hold values 0101, only
No-PI and NrP3 are turned on. This creates a set of two
latches that are disconnected by NrPo and NrP2• Likewise,
when the cell holds logic 1, two pairs of inverters, NrP0 and
NrP], are turned on while the other two pairs of inverters,
No-PI and NrP3, are turned off.
With this is mind, consider the case where the cell is
holding a logic 0 (XO . . . x3=0101). In this situation, the
horizontal inverter pairs, No-PI and NrP3, are turned on
while the two vertical pairs are turned off. If a negative
upset event were to affect one of the nodes, x" a change in
state of Xi+1 could be induced through Pi+l. The potential
change at X,+I would be blocked from changing the state of
Xi+2 due to Px+2• Also, the event at Xi would not be able to
induce a change of state at Xt_1 because a value of 0 at X,
would only turn off Nt_1 without changing the state of Xi-I.
Once the transient event ends, Xi_/ and X,+2 are able to 3. NCL Gate Development
restore X, and x,+/ to their original states.

A similar situation occurs when the cell is in a logic 1 state,
where Xo through X3 have a value of 1010, and a positive
upset event affects one of the nodes, Xi. In this case, Nx./ is
turned on while Px+/ is turned off, which prevents Xi from
changing Xi+/. This allows the event to potentially upset Xi./.
Even if Xi./ is upset, x,./ is unable to transmit the incorrect
data through N,_2. Again, once the event subsides, x,+/ and
X,+2 are able to return X, and x,-/ to their original states.
As later shown in the paper, a DICE latch provides a
valuable alternative to a typical latch for a radiation-exposed
environment. When combined with the delay-insensitivity
of NCL, a stable and reliable device is created for data
storage.
Schematic Development
Each NCL gates uses the standard NFETs and PFETs from
the IBM 9HP kit. The channel-length for each PFET device
is the minimum, which is 100 nm, and the channel-width for
most PFET devices is 120 nm. In order to improve the
cryogenic temperature reliability of NFET devices, their
channel-length is doubled to 200 nm while also using the
120 nm minimum size for channel widths. Sizing of each
gate is determined by averaging the output drive capacitance
while using minimum channel-width devices and the input
combinations that cause the slowest rise and fall of the
output. In order to find the output drive capacitance for each
gate the rise and fall times are measured when the output
drives two average size gates (two TH22 gates are used for
this library).

0 0

a -1L a -1L
0 o .

a b-{�L z -{ =� c .
z
b 0 J
+

b--1b z --1b
0 0

<

a- Ie a

Figure 3: TH22 gate schematic

Table 1: Table of NCL gates

THl2 THl2b TH13 TH13b TH14 TH14b

TH22 TH22n TH23 TH24 TH24comp TH24w2
TH24w22 TH33 TH33n TH33w2 TH34 TH34w2
TH34w3 TH34w22 TH34w32 TH44 TH44w2 TH44w3
TH44w22 TH44w322 TH54w22 TH54w32 TH54w322

3
The rise and fall times for each gate's output were measured
using the transistor threshold voltage, which is found using
a voltage divider. The voltage divider is tested through a
range of temperatures from -196° C to 125° C. Each
threshold is around 560 mY. The highest and lowest
threshold voltages are found at -196° C and 125° C,
respectively.
Once the average among all gates for the fall time and rise
time is found, the slower of the two is selected as the rise
and fall timing requirement for each gate's output. Each
gate's PFET and NFET channel-widths are then adjusted
until the fall and rise times meet the decided requirement.
For this library, the output rise and fall time requirement is
369 ps. Now that a timing requirement has been selected, a
capacitor replaces the two gates that the test gate drives.
This capacitor is increased or decreased until the measured
output rise and fall times match the results of the test using
two TH22 gates. In the case of this library, a 6 tF capacitor
is selected. Each gate output now has to drive a 6 tF
capacitor with a fall and rise time of 369 ps or less. For each
gate that does not meet this requirement, the NFET and
PFET channel-widths are increased until the fall and rise
time for each input combination is as at most 369 ps. The
pull-down and pull-up networks are also adjusted if one
performs faster than the other in order to provide a
consistent performance.
This process ensures that all gates meet the minimum output
rise and fall times regardless of the input combination. It
also prevents gates from being oversized such that they
needlessly use more power than required. Table 1 shows all
NCL gates in this library.
Figure 4: TH22 gate layout
4
Layout Development
Each gate in the library uses a layout template that is
designed to be modular in that it can easily be extended to
add more devices. Figure 4 shows the layout of a TH22 gate
with the corresponding schematic in Figure 3.
The height of each cell is fixed while the width is adjusted
in order to accommodate space required for additional
devices. If the channel-width of a device exceeds the
maximum allowed by the height of the template cell, the
device is split into mUltiple fingers where the width of each
finger is at or below the maximum width. This configuration
allows for a maximum single-fmger NFET channel-width to
be 590 nm, and a maximum single-fingered PFET channel­
width to be 1160 nm. To further increase the radiation­
hardness of each gate, a guardring is placed around each
transistor [7]. Each guardring contains as many substrate
contacts as allowed by the setup and routing of the devices.
This design helps to prevent ionizing-radiation events from
affecting multiple devices as well as mitigating the effects
of an event occurring outside of the gate.
The layout shown in Figure 4 places NFET devices at the
bottom of the cell and PFET devices at the top of the cell.
The cell is set up such that the input rails (Ml, blue layer),
which are used to connect the inputs to the devices, run
horizontally above the PFETs and below the NFETs. The
Ml sections containing all of the substrate contacts are
VDD (surrounds the PFETs in the top section of the
template) and GND (surrounds the NFETs in the bottom
section of the template). VDD also runs horizontally with
Ml above the drain and source of each of the PFETs, but
below the input rails located above the PFETs. Likewise,
GND runs horizontally in Ml just below the sources and
drains of the NFETs but above the space allowed for adding
an input rail below the NFETs.
Since the guardrings prevent the polysilicon (red layer) of
an NFET and a PFET from connecting directly, the second
metal layer (M2, purple layer) runs vertically to connect the
gates of an NFET and PFET. This allows the space between
the NFETs and PFETs to be used for routing between the
internal nodes of a gate using Ml.
Aside from using M2 for connecting the gates of two
devices, it is only used when the internal nodes of the gate
cannot be routed using Ml. Depending on the routing and
the number of devices, some of the area between the NFETs
and PFETs may be unused. With this setup, though, all of
the NCL gates can be laid out without increasing the height
of the cell. For gates that use fewer inputs, and therefore
have more space for the first metal layer above the PFETs
and below the NFETs, more substrate contacts are added to
the guardrings in the area that splits the devices. For
example, in the TH22 gate layout, it can be seen that the
first PFET on the left only has one Ml input rail, input
signal a. As a result, three more substrate contacts can be
buffers where the first buffer's internal node, alnverted, is
connected to a capacitor, CO. The capacitor in combination
with the first inverter provides the delay for a delay element.
If more delay is required, the channel-width of the
transistors in the first inverter of the first buffer can be tuned
to cause the capacitor to charge or discharge more slowly.
Also, if a slow rise time and fast fall time are required, the
inverter between a and alnverted can be adjusted such that
the channel width of the NFET is much larger than the
PFET, allowing slow charging and fast discharging.
One concern for the delay chains in using capacitors is that
the output will rise and fall too slowly. This can be easily
alleviated by adding a buffer, consisting of large channel­
width FETs, to the output of the buffer driving the capacitor.
• Iz • Imid • la
1.25
1.0
.75
�.5
0>-

added to the side of the guardring that splits the first and
second PFET.
.25

4. Delay Elements
0.0 )

In order to provide reliable delay, radiation-immune and

temperature-stable DMIM-capacitor-based delay elements
-.25 I I I I I I
are designed. Using these capacitors in the 9HP process I , i I I I I , I i I I I I

10.0 15.0 20.0 25.0 30.0 35.0

provides several advantages: the capacitors are naturally time (ns)
radiation-hardened and temperature-stable, and due to the Figure 5: Delay element simulation
layers that the capacitors use in the 9HP process, a buffer
can be placed directly underneath the capacitor. Figure 6
shows a schematic of a delay element, which consists of two

a alnverted mid z

co

Figure 6: Delay element schematic

5
This is shown in Figure 5 where the schematic in Figure 6 is
simulated. This design prqovides a 3 ns delay between the
rise of signals a and z, and a 4 ns second delay between the
fall of a and z. CO has a capacitance value of 263.789 fF,
which is the capacitance of the unit size capacitor chosen for
this library. The fIrst buffer contains a connection to a
capacitor from the input of the second inverter (node
alnverted).
Figure 7: Buffer and capacitor layout
The output of this buffer is shown by signal mid in Figure 5,
where the rise and fall times are simulated to be 0.808 ns
and l.151 ns. Even though this result is functionally correct,
both the rise and fall time are slower than the chosen 369 ps
requirement. The slow rise and fall times are drastically
improved by adding a second buffer, containing just two
inverters and zero capacitors, which gives the output signal
z shown in the output waveform in Figure 5.
With the additional buffer, the rise and fall times of the
output signal z are now 39.8 ps and 47.74 ps, more than
satisfy the 369 ps requirement. The channel widths of the
devices in the second buffer could even be decreased to save
power while still meeting the time requirement.
The schematic demonstrates another advantage provided by
this type of a delay element: the delay between the rise and
6
fall of a to z can be can be tuned to be equivalent or largely
different. In one example of a delay element, a 20 ns delay
exists between the rise of the input and rise of the output
while only a 4 ns delay is provided between the fall of the
input and the fall of the output. This functionality is created
by adjusting the NFETs and PFETs connected to the
capacitor attached to alnverted. Of course, more than one
delay element can be chained together to provide larger
delays.
Another advantage in using delay elements is that the layout
of a capacitor can be created in the higher levels of metal,
which are not used by the buffers. This allows buffers to be
placed directly underneath the layout of a capacitor, which
is shown in Figure 7. As illustrated, the buffer in the lower
left-hand comer is about nine times smaller in area than the
capacitor. Because of this, multiple buffers can be placed
under the capacitor, or any other NCL gate required in a
circuit.
As a result, capacitor-based delay elements not only provide
radiation-hardness and reliability across a wide temperature
range, but also are area effIcient.
5. Asynchronous Storage Devices
Asynchronous DFF
In a synchronous environment, the clock signal controls the
storage of data in a DFF. Since an NCL circuit does not use
a clock signal, a traditional DFF is modified such that a
dual-rail data can be used as the data input signal and to
control the clock input signal [8]. In order to accomplish
this, an additional output from the input of the second latch
in the DFF is created, qint. This node changes based on the
value of the data input when the clock signal is low.
If rail' of the dual-rail data value is connected to the data
input of the DFF when the clock signal is low, qint will
reflect its value after the input propagates through the latch.
Once qint's value changes to the value of rail' of the input
data, qint is then used in combination with both rails of the
input data to cause the clock signal to rise. The input to the
clock signal is designed such that only data that has a value
of DATAO or DATAl can enable the clock signal. This
design prevents NULL waves from changing data stored in
these DFFs. Using this method of clocking in data also
ensures that the required setup time for the data input signal
of the DFF is met and that only a DATA value can update
the data in the register.
Figure 8 is a simulation of the asynchronous DFF that
shows the correct operation using railo, RO, and rail' , Rl, of
the input for controlling the clock signal, elk, as well as
providing the data input for the DFF.
 ·/rst intended, a NULL value has no effect on q or qb. The DFF

� �::: � CJ :�:; �J' ::�,W'�� ;::�,�::��":' :�: �<:�..�: ;::�� :�:

behaves correctly across the temperature range of -1960 C to
1250 C.

�
�
1.5 � •
""",
19b
" """ , " DICE Based Asynchronous DFF
;.:.�'::'" ...... ....... .
:> .25
_ ;':", '"
While the asynchronous DFF is fully functional and reliable
over the temperature range of -1960 C to 1250 C, it is
, .. :::1,::::::;: susceptible to SEUs from ionizing radiation. In order to
solve this issue, a DICE-based asynchronous DFF is
proposed.

Figure 9 shows the schematic of the DICE-based

• Igint
:::,,: "",,::::,::,,/,,� : : J >" :::::L
asynchronous DFF, which, while using the same setup as
� �::: � ; ' : " : ,,: : : :: ":': the previous DFF in order to control the clock input signal,
replaces the latches with two transmission-based DICE
IRO
2: 1.25 =3 i::
latches. This DFF is functionally the same as the
asynchronous DFF; a dual-rail data controls the data input
:>-.253 ;" as well as the elk signal with the aid of the internal node

: ' , " , ,,;, , ""," . ' "

./R1 qint. Because of the design of the DICE latches, a higher
2: 1.25 =3 ::
253
""": ;:J:: " , "" : L drive capacitance is required for the input to each latch,
� -+
which is why there are two buffers between qint and
ir
" , '�---r--'-'--
'j-r, --.--.--,' -jr-T,---r
-r ',
";- ,
"j '-"',
; "--,"'-':,
:':_
' '
" 'j
r-T''
'
qintBufJered. QintBufJered is the buffered value of qint that
0.0 25.0 50.0 75.0 100.0
time (ns) drives the data input to the second latch. Nodes q, qb,
Figure 8: Asynchronous DFF simulation diceNodeC, and diceNodeD are labeled in the schematic
because they correspond to nodes Xo, XI, X], and X3,
It is shown that elk only rises when the dual-rail data input respectively, in Figure 2.
is DATA and the active-high reset is low. Once elk rises, q,
the data output of the register, only rises if the input is
DATAl, just as a traditional DFF only outputs logic 1 if the
input is 1 when the clock rises. It can also be seen that, as

qintBuffered
I, rst

t
q
qb

GND
i6Pln :t rst

Figure 9: DICE-based asynchronous DFF schematic

7
 6. Radiation Analysis tolerant to all radiation events up to an LET of 100. The
results for both devices are shown in Table 3.

In analyzing the resulting behavior from radiation events in Table 4: Number of upsets per component per LET
each cell, the SET model leverages the worst-case upset value
using a double-exponential function [9]. Each cell is LET value Asynchronous DFF DICE DFF
simulated in which the channel widths and location of
20 20 0
vulnerable devices can be adjusted to improve SEU
50 20 0
tolerance.
70 21 0
100 21 0
For NCL gates, a few examples are shown in Table 3. The
simulation shows the number of affected transistors that
Results show that in every case the DICE-based DFF
caused the upset. The number of upsets per gate is a result
recovers from an SET. Figure 10 shows diceNodeD (refer to
of as many as 80,000 passes in simulation.
Figure 9) which corresponds to node X3 in Figure 2. The
graph on the left is a magnification of the activity resulting
Table 3: NCL gate simulations results showing the
from the SETs during time 4.36e-8 to 4.44e-8 in the graph
number of upsets per LET va Iue
on the right. The legend shows the LET values for each
Gates LET = 1 LET-5 LET-20
curve. While each increasing LET simulation value takes an
TH33 30 36 36
increasingly longer amount of time to recover, no events
TH44w22 87 97 III
resulted in an upset. This shows that the feedback
TH54w32 53 62 64
mechanism in each DICE latch is working as intended,
TH44w3 45 56 56 providing a higher level of radiation-tolerance for these
THl4b 0 0 0 asynchronous storage devices.
THl2 0 0 0
THl4 0 0 0

The results of the simulations between the asynchronous

DFF and DICE-based asynchronous DFF show that despite
an area penalty, the DICE-based asynchronous DFF is

1.2 70 100
50 -
1
1.0 20 -
5
1.0

0.8 0.8
Q) Q)
01 01
2 0.6 � 0.6
0
g >

0.4 0.4

0.2
0.2

0.0
0.0 b==1==±:=:=±;:::::C;�?:=::;:::i;=;==;:
9
4.34 4.36 4.38 4.40 4.42 4.44 4.46 4.48 3.5
time 1e-8 time 1e-8
Figure 10: Simulation results for diceNodeD of the DICE-based DFF

8
 7. Conclusion
An asynchronous NCL library provides many advantages
for integrated circuits operating in a space application where
temperature reliability and radiation tolerance is required. It
is shown that an NCL gate library can provide circuit
reliability in a temperature range of -196° C to 125° C. The
delay insensitivity allows each gate to operate reliably,
regardless of how much each device's performance is
changed due to temperature fluctuations. Each NCL gate
shows varying performance when simulated with LETs of
up to 100 MeV*cm2!mg.
In addition, capacitor-based delay elements provide a
modular method for creating necessary delay that is both
temperature-stable and radiation tolerant. Due to the layout
of the DMIM capacitors in the IBM 9HP process, the layout
of the delay elements is area-efficient. Using capacitors also
provides radiation-tolerance to each delay element, as well
as increased stability across a wide temperature range.
[3] John Brady and J. Di, "Radiation-Hardened Delay­
Insensitive Asynchronous Circuits," Single Event
Effects Symposium, May 2014.
[4] Karl M. Fant, and Scott A. Brantd, "NULL Convention
Logic: a complete and consistent logic for
asynchronous digital circuit synthesis." in ASAP 96,
Chicago, IL, Aug. 1996.
[5] S. C. Smith and J. Di, "Designing Asynchronous
Circuits using NULL Convention Logic (NCL),"
Morgan Claypool Publishers, 2009.
[6] T. Calin, M. Nicolaidis, and R. Velazco, "Upset
hardened design for submicron CMOS technology,"
IEEE-Transactions on Nuclear Science, vol. 43, no.6,
pp. 2874-2878, Dec. 1996.
[7] John D. Cressler and H. Alan Mantooth, Extreme
Environment Electronics. Boca Raton, FL: CRC Press,
2012, ch. 43.

For data storage in an asynchronous environment, an
asynchronous DFF is shown that behaves correctly for
storing dual-rail logic data. Despite its correct behavior
across a wide temperature range, it is susceptible to
ionizing-radiation events. To improve this design for a
radiation-exposed environment, a DICE latch based
asynchronous DFF is proposed. Using DICE latches
prevents radiation-induced events from upsetting the overall
state of the DFF, and the resulting storage and propagation
of corrupted data. The simulation of this DICE-based DFF
results in 0 upsets when subjected to LETs of up to 100
MeV*cm2!mg.
[8] Michael Hinds, "A Low Power Asynchronous MSP430
Microcontroller," Ph.D. dissertation, University of
Arkansas, Fayetteville, AR 7270 I.
[9] A. Matt Francis, Dimitre Dimitrov, Jeff Kauppilla,
Andrew Sternberg, Michael Alles, James Holmes, and
H. Alan Mantooth, "Significance of Strike Model in
Circuit-Level Prediction of Charge Sharing Upsets," in
IEEE Transactions on Nuclear Science, Vol. 56, No. 6,
December 2009.

Acknowledgements

The authors would like to gratefully acknowledge the

support for this research under the NASA STRO-ESI
program (Award #NNX14AB03G). Also, they would like to
thank Dr. John Cressler for his contribution of the cold­
temperature FET simulation models.

References

[I] P. Shepherd, S. C. Smith, J. Holmes, A. M. Francis, N.

Chiolino, and H. A. Mantooth, "A Robust, Wide­
Temperature Data Transmission System for Space
Environments," in Proceedings of the IEEE Aerospace
Conference, Big Sky, Mt, 2013.

[2] B. Hollosi, M. Barlow, Guoyuan Fu, C. Lee, Jia Di, S.

C. Smith, H. A. Mantooth, and M. Schupbach, "Delay­
insensitive asynchronous ALU for cryogenic
temperature environments," 2008, pp.322-325.

9
 Biographies
John Brady received B. S and MS degrees in
Computer Engineeringfrom the University of
Arkansas in 2012 and 2014, respectively. He
is currently pursuing a Ph. D. in Computer
Engineering with an expected graduation date
of 2017. John has worked in research since
2011 under Professor Di in the CSCE
department. His research topics include asynchronous
integrated circuit design, radiation hardening, and
hardware security. He is a member of Tau Beta Pi honor
society.
A. Matt Francis holds B. SE. E. (5103) , B. S.
Physics (12104) , MSE. E. (5107) and Ph. D.
(5109) degrees allfrom the University of
Arkansas. Dr. Francis founded Ozark
Integrated Circuits in 2011 and serves as
President and CEO. At Ozark IC he has
applied his expertise in extreme
environments, IC design and modeling to the development
of cutting-edge designflows and custom ICs for customers
using novel design approaches and technologies. These
include asynchronous digital logic, high-temperature SOl,
and integrated SiC electronics. From 2004 to 2010 Dr.
Francis served as Applications Consultant (extreme
environments) at Lynguent, where he designed and
implemented compact modeling toolkits covering BSIM3,
BSIM4 and BSIMSOI and developed the industry first
radiation-enabled BSIM4 compact modeling capability for
90nm technology. Dr. Francis also serves as an adjunct
Professor in Electrical Engineering at the University of
Arkansas, as a member of IEEE, and is a member of Eta
Kappa Nu and Tau Beta Pi honor societies.
Jim Holmes is an expert in electronic
design automation with 20 years of
experience the deep submicron design
domain. From 2006 to 2011 he was Vice­
President of Research and Applications
Consulting at Lynguent, Inc. were his
background in ASIC verification was applied to automation
of model based design techniques. From 1992 to 2006 Jim
was an AnaloglMixed Signal System-on-Chip modeling and
simulation specialist for Texas Instruments. He enabled
validation and verification activities on over 40 SoCs
spanning consumer applications from servo control in hard
disk drives to baseband processing in cellular phones. Jim
was elected Tl Senior Member Technical Staff in 2004.
Sincejoining Ozark IC in 2012 as IC Technologist he has
led development of OziC's high-fidelity, low-cost design
flow for extreme environments and development of hardened
IP modules. He holds BSEE (5190) and MSEE (5192)
degrees from the University of Connecticut.
10
Jia Di received B. S and MS degrees from
Tsinghua University, China, in 1997 and
2000, respectively. He completed his Ph. D.
in Electrical Engineering at the University
of Central Florida in 2004. He thenjoined
the Computer Science and Computer
Engineering Department of the University
of Arkansas in August 2004, where he is
now a Professor. His research area is asynchronous
integrated circuit design for various applications including
extreme temperature, ultra-low power, radiation hardening,
and hardware security. He is a senior member of IEEE and
a member of the National Academy of Inventors.
H. Alan Mantooth (S'83 - M'90 - SM'97 -
F'09) received the B. S. (summa cum laude) and
M S degrees in electrical engineeringfrom
the University of Arkansas in 1985 and 1987,
respectively, and the Ph. D. degreefrom the
Georgia Institute of Technology in 1990. He
joined Analogy in 1990 where he focused on semiconductor
device modeling and the research and development of HDL­
based modeling tools and techniques. In 1998, hejoined the
faculty of the Department of Electrical Engineering at the
University of Arkansas, Fayetteville, as an Associate
Professor. Dr. Mantooth helped establish the National
Center for Reliable Electric Power Transmission (NCREPT)
at the UA in 2005, for which he serves as director.
Professor Mantooth serves as the Executive Director for
NCREPT as well as two of its constitutive centers of
excellence: the NSF IIUCRC on GRid-connected Advanced
Power Electronic Systems (GRAPES) and the NSF
Vertically-Integrated Center on Transformative Energy
Research (VICTER) . In 2006 he was selected as the
inaugural holder of the 21st Century Endowed Chair in
Mixed-Signal iC Design and CAD. Dr. Mantooth has
published over 200 refereed articles and three books on
modeling, power electronics and IC design. Dr. Mantooth is
a Fellow of IEEE, a member of Tau Beta Pi and Eta Kappa
Nu, and registered professional engineer in Arkansas.