Course: Electronics – for Complete Beginners

Section 6: Solid State Devices

Lecture 5: Field-Effect Transistors-MOSFETs

MOSFET Field Effect Transistors

The next-generation FET, the
Metal-Oxide-Semiconductor Field-Effect
Transistor, or MOSFET, was developed at
Bell Labs in 1960 by Korean-born Dawon
Kahng working under the Egyptian-born
researcher Martin Atalla.
After its slow acceptance by Bell Labs and
the electronics industry, the MOSFET has
stolen the thunder from the JFET, becoming
the most widely used type of semiconductor
device in the computer and electronics
industries.
Good news! — It also happens that the
workings of the MOSFET are much easier
to grasp than the BJT and the JFET at the
most fundamental level.
Instead of a p-n junction, the MOSFET’s
gate is insulated from the current-carrying
channel by a very thin layer of metal oxide.
The gate acts somewhat like the plate of a
capacitor. Since there is no DC current flow
through the gate, MOSFETs dissipate much
less power, and have very high input

impedance.
In the enhancement mode MOSFET,
n-type source and drain regions are diffused
into a p-type substrate. The p-type substrate
is very lightly doped, and therefore has a
very high resistance. With zero voltage on
the gate, current cannot pass between the
source and drain.
A positive potential at the gate creates a
strong electric field across the p-type
substrate, even for relatively small gate
voltages. This positive charge repels the
positive charges (holes) in the p-type region,
and attracts the negatively charged electrons,
causing them to populate a small band
within the gate-substrate interface.

As the gate voltage increases, this n-type

band widens, ultimately connecting the
n-type source and drain regions. This
provides a channel for current flow from the
source to the drain, so this is called a
n-channel device.
The gate voltage at which this occurs is
called the threshold voltage, Vth, which is
ordinarily only about 0.7V to 1V for an
n-channel low-voltage logic-compatible
MOSFET, and twice that for high voltage
power devices.
 Increasing the gate voltage beyond the
threshold voltage results in a corresponding
increase in the current-carrying ability of the
channel, until the saturation point is
reached. Further increases in the gate
voltage then have little effect on drain
current.
Since the gate is strictly voltage-driven,
drawing no current, the MOSFET actually
requires only minimal attention to design
parameters when used in switching
applications. Reliable operation depends
only upon ensuring that the “on” and “off”
gate potentials swing well across Vth,
whether going from low to high, or high to
low, and are high enough in the “on”
condition to ensure saturation.
Power MOSFETs
MOSFET technology has come a long
way over the past several decades, with
robust SiC MOSFET (Silicon Carbide)
power modules now controlling kilovolt
power levels and hundreds of amps. That’s
not the kind of “power MOSFET” that we’re
interested in, however. That takes one into
the realm of electric power generation and
control, so we won’t be going there.
For our purposes, the power MOSFET is
distinguished from the kind of MOSFETs
that we’ve been talking about so far, what
we’ll call small-signal MOSFETs, by
architecture.
The structure thus far illustrated is the
lateral or planar structure, a design that is
suitable for signal-level discrete components
and monolithic integrated circuits. Higher
power applications need better
voltage-blocking capabilities, which requires
increasing the distance between the source
and drain. To achieve that, new vertical
structures were developed, the most
successful being the D-MOSFET. For our
purposes, that will be what distinguishes
signal-level MOSFETs and power MOSETs.
In the vertical structure, the current path is
created underneath the gate in the same way
as in the lateral MOSFETs. Source current
flows underneath this gate area, but then

vertically through the drain, spreading out as

it flows down through many thousands of
N+ sources conducting in parallel.
The vertical geometry results in much
higher blocking voltage capabilities, much
lower on-state resistances, and faster
switching than the lateral MOSFETs.
 Power MOSFETs have also been
developed which can be operated by
low-level output devices, such as
microcontrollers. These are called
logic-level power MOSFETs to distinguish
them from regular power MOSFETs, which
usually have higher control voltage
requirements. These should not be confused
with the planar signal-level devices, which
are commonly used in the manufacture of
low-level logic ICs.
Schematic Symbols
Notice the distinctions between the
schematic symbols for MOSFETs …

Discrete MOSFETs are usually depicted

symbolically with a substrate contact
(sometimes called the body or bulk terminal)
with an arrowhead pointing inward for
n-type transistors, and outward for the
p-type. The substrate is usually connected
internally to the source, the transistor
actually being a three-terminal device.
In diagrams of integrated circuits, the
substrate connection is often omitted for the
sake of simplification, with the symbol
altered as shown here.
MOSFET Applications
Revisiting the relay driver circuit example
of the previous lecture, replacing the BJT
with a depletion mode JFET would not be
wise, since a loss of its control signal would
result in the output being on all the time —
an unacceptable failsafe situation. A
n-channel enhancement mode MOSFET, on
the other hand, would readily fill the bill …

Depletion mode MOSFETs, which are less

commonly used, include a surface impurity
layer of opposite type to the substrate, the
conductivity of which is decreased by
application of a negative voltage to the gate,
which generates a field that depletes carriers
from that layer.
In either case — enhancement or depletion
— p-channel devices are simply mirror
images of the n-channel versions, with
n-type substrates and p-type source and
drain diffusions. The bias voltages used are
therefore also reversed.
For brevity’s sake, “n-type MOSFET” is
often referred to as n-channel, with its
compliment being called p-channel.

In this example, a p-type MOSFET

(p-channel) transistor is used as a load
switch. Load switches extend battery life in
notebooks, cell phones, hand held gaming
systems and many other portable devices by
enabling the system to distribute power only
to peripherals or sub-circuits currently in
use. Each little switch connects or
disconnects the supply voltage to a specific
load.
 A logic signal from the system power
management control circuitry turns the load
switch on and off by means of the
small-signal n-channel transistor. When the
control signal is LOW, the n-channel
transistor is off and the gate of the p-channel
pass transistor is pulled up to VIN. When the
control signal goes high, the n-channel
transistor turns on, which pulls the gate of
the pass transistor to ground, turning it on to
apply power to the load.
As long as VIN is higher than the threshold
voltage of the p-channel transistor, it will
turn on when the control signal goes high
without the need of any additional bias
voltage source. The resistor is selected so
that a few milliamps of current will flow
through the drain of the n-channel transistor
when it is turned on. Depending on V+,
anything from 1K to 10K will usually do.
 In practical applications, the small-signal
n-channel transistor is often integrated into
the same package as the pass transistor.
CMOS
The “C” stands for complimentary,
referring to a configuration where n-type
and p-type MOSFET transistors work
together to perform a desired function.
Originally referred to as “Low Stand-By
Power Complementary Field Effect
Circuitry”, the idea was developed at
Fairchild Semiconductor in 1963 by Frank
Wanlass. The company unwisely opted
against doing anything further with it.
Five years later, RCA launched its Series
4000 line of COS/MOS logic chips, which
rapidly became an industry standard. They
offered the advantages of very low power
consumption, compatibility with a range of
supply voltages from 3V to 15V, high noise
immunity, and simpler circuit design, since
fan-out concerns — meaning the number of
inputs that could be driven from a single
output — essentially became a thing of the
past. The downside was their slow speed,
about one tenth that of the popular TTL
logic, and vulnerability to static discharge,
both of which RCA eventually remedied,
replacing TTL circuits in many applications.
CMOS technology is used mainly in
digital applications. Besides revolutionizing
common logic gates, it is now used in
large-scale applications such as
microprocessors, microcontrollers, static
RAM, and complex digital logic circuits. It
is less commonly used for analog circuits.
The simple inverter, or NOT gate,
illustrates the CMOS principle …
 In logic applications, the MOSFETs can
be viewed simply as voltage-actuated
switches.
In this case, when the input signal is low,
the p-channel transistor is biased on,
providing a low-resistance connection
between V+ and the output. At the same
time, with 0V on its gate, the n-channel
transistor is biased off.
When the input signal switches from low
to high, the p-channel transistor becomes
biased off. The n-channel transistor is now
turned on, providing a low resistance path to
ground.
The insulated gates of MOSFETs are very
high impedance inputs, drawing only
minimal current to charge and discharge
gate capacitances. In addition to that, there
will also be a very brief transition current, as
the two transistors pass through their
respective linear regions while switching
states. But otherwise, assuming that the
output will be driving other CMOS inputs,
there is no current flow going on during
times when the circuit is resting in one state
or the other. Hence the very low power
dissipation characteristic of CMOS logic. In
chips that might include thousands, or tens
of thousands of transistors, this is a very
important advantage!
CMOS Logic
Logic circuits work in the binary realm,
with 0s and 1s. The NAND gate compares
its inputs, providing an output when they’re
all at a logical “1” …
 In this example, logical 0 is low; at or near
ground potential. Logical 1 is high, at or
near V+. By inspection, you can deduce that
whenever input A or input B is low, one of
the n-channel transistors will be off, and one
of the p-channel transistors will be on,
causing the output to be high, or logical “1”.
When both inputs happen to be high, both
p-channel transistors will be off, and both
n-channel transistors will be on, thereby
connecting the output to ground — the low
output condition.
Two-input NAND gates are common, but
they can actually have any number of inputs.
It’s only a matter of adding more p-channel
transistors in the parallel group, and more
n-channel types in the series group — pairs
of complementary n- and p-type MOSFET
transistors, in other words.
CMOS Memory
CMOS is also used to construct SRAM —
(static random-access memory) arrays. A
single cell, consisting of six transistors,
holds a single bit, so a 1Mb CMOS memory
chip has over 6-million transistors!

Each cell consists of two access switches,

Q5 and Q6, and two simple inverters,
connected back-to-back, the output of
Q1/Q2 connected to the input of Q3/Q4, and
vice versa.
The cells are accessed for writing and
reading individually by the “word line”
(WL) which is controlled by an address
decoder.
To set the contents of the cell, the “bit
line” (BL) is set to the appropriate value, a
“1” or a “0” with the compliment of that
appearing on the “bar-bit line” (BL
¯¯). WL is
then taken high (logical 1), which turns on
Q5 and Q6. The bit line drivers simply
overpower the weaker inverter transistors,
forcing the values on BL and (BL¯¯) into their
inputs. WL then goes low again (logical 0)
leaving the cell in the standby mode.
For example, if BL is high when WL is
asserted, Q4 will be switched on, and Q3
will be switched off. The output of that
inverter will therefore be “0” and that will
be the input to the Q1/Q2 inverter.
Meanwhile, since BL is high, (BL¯¯) will be
low, and that will also force the output of the
Q1/Q2 inverter to go high; to logical 1.
In the standby mode, either Q1 or Q3 will
be left switched on which, in turn, will
enable either Q4 or Q2, thereby holding the
inverters in the condition they were in when
WL last went low. The cell will hold its
contents in that manner indefinitely so long
as the system has V+ power.
 The read operation involves switching the
BL and (BL
¯¯) lines to “read” mode, and then
asserting WL. The contents of the cell can
then be sensed on the bit lines through Q5
and Q6.
Notice the chief advantages — no
refreshing required, and no power
dissipation in these cells in the standby
mode.
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Triggered solid state devices will be the
subject of the next lecture in this section.
These include SCRs, DIACs, TRIACs, and
similar devices, which are most often found
useful for electrical power control
applications.
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