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Introduction to
Power semiconductors
Brainstorming
• Circuit diagrams?
• V-I characteristics?
• Switching time(“on” “of”) characteristics:
Todays lecture outcomes
The students will be able to:
• Explain elements of semi conductor devices
• Explain operation principles of power
semiconductor devices
• Differentiate semiconductor devices based on
their application
Definition
5
Some of the features of the most common power semiconductors are listed below
Some applications of power electronics
Commercial applications: heating systems ventilating, air
conditioners, central refrigeration, lighting, computers
and office equipment, uninterruptible power supplies
(ups), elevators, and emergency lamps.
This causes a small voltage drop across the device (<1 V), which
under ideal conditions is usually ignored. By contrast, when a
diode is reverse biased, it does not conduct and the diode then
experiences a small current flowing in the reverse direction called
the leakage current.
Once the applied voltage is over this limit, the current will
increase rapidly to a very high value limited only by an
external resistance.
Power transistors
Most of the power electronics applications use npn transistor because electrons move
faster than holes, and therefore, npn transistors have considerable faster commutation
times.
,
MOSFET
• What is mosfet? Who can draw the ckt?
• How can you differentiate with BJT?
• Where it will be applied?
POWER MOSFET
Insulated Gate Field Effect Transistor ( IGFET) is :
A Transistor whose Gate input is electrically insulated from the main current
carrying channel
most common IGFET is Metal Oxide Semiconductor Field Effect Transistor
(MOSFET)
MOSFETs are three terminal devices with a Gate, Drain and Source and both P-
channel (PMOS) and N-channel (NMOS) MOSFETs are available. MOSFETs are
available in two basic forms:
Depletion Type – the transistor requires the Gate-Source voltage, ( VGS ) to
switch the device “OFF”. The depletion mode MOSFET is equivalent to a
“Normally Closed” switch.
The more negative the bias, the higher the rate of recombination.
The resulting level of drain current is therefore reduced with
increasing negative bias for VGS
There are in fact two reverse-biased p-n junctions between the n-doped regions and the p-
substrate to oppose any significant flow between drain and source.
Increasing this positive gate voltage will cause the
channel resistance to decrease further causing an
increase in the drain current, ID through the channel.
In other words, for an n-channel enhancement mode
MOSFET: +VGS turns the transistor “ON”, while a zero or
-VGS turns the transistor “OFF”. Then, the
enhancement-mode MOSFET is equivalent to a
“normally-open” switch.
The reverse is true for the p-channel enhancement
MOS transistor. When VGS = 0 the device is “OFF” and
the channel is open.
The application of a negative (-ve) gate voltage to the
p-type eMOSFET enhances the channels conductivity
turning it “ON”.
Then for an p-channel enhancement mode MOSFET: +VGS turns
• Enhancement-mode MOSFETs make excellent
electronics switches due to their low “ON”
resistance and extremely high “OFF” resistance as
well as their infinitely high input resistance due to
their isolated gate.
• Enhancement-mode MOSFETs are used in
integrated circuits to produce CMOS type
Logic Gates and power switching circuits in the
form of as PMOS (P-channel) and NMOS (N-
channel) gates.
• CMOS actually stands for Complementary MOS
meaning that the logic device has both PMOS and
NMOS within its design
p-Channel Enhancement-Type MOSFETs
Insulated Gate Bipolar Transistor(IGBT)
36
Terminal Characteristics of SCR
38
Working principles of SCR
I. When gate is open.
Fig. shows the SCR circuit with gate open i.e. no voltage applied to
the gate. Under this condition, junction J2 is reverse biased while
junctions J1 and J3 are forward biased.
Hence, the situation in the junctions J1 and J3 is just as in a npn
transistor with base open. Consequently, no current flows through
the load RL and the SCR is cut off.
However, if the applied voltage is gradually increased, a stage is
reached when reverse biased junction J2 breaks down.
The SCR now conducts heavily and is said to be in the ON state. The
applied voltage at which SCR conducts heavily without gate voltage
is called Breakover voltage.
(ii) When gate is positive w.r.t. cathode.
The SCR can be made to conduct heavily at smaller applied voltage
by applying a small positive potential to the gate as shown in Fig
below
An SCR has two states i.e. either it does not conduct or it conducts
heavily. There is no state in between. Therefore, SCR behaves like a
switch.
There are two ways to turn on the SCR. The first method is to keep
the gate open and make the supply voltage equal to the break over
voltage.
The second method is to operate SCR with supply voltage less than
break over voltage and then turn it on by means of a small voltage (
typically 1.5 V, 30 mA) applied to the gate.
VAA K
VGG
Fig. Circuit
48
dv
High dt Triggering:
• Under transient conditions, the capacitances of the p-n
junction will influence the characteristics of a thyristor.
• If the thyristor is in the blocking state, a rapidly rising voltage
applied across the device would cause a high current to flow
through the device resulting in turn-on.
• If ij2 is the current through the junction J2 and Cj2 is the
junction capacitance, and Vj2 is the voltage across J2 , then a
high value of charging current may damage the thyristor and
the device must be protected against high
dq2 d C j2 dVJ 2 dC j2
ij 2 C j Vj V j2
dt dt 2 2
dt dt
dv
From the above equation, we see that if is large, ij2 will be large
dt
49
GATE TRIGGERING CIRCUITS
Gate triggering circuit consists of two main circuits
1. A pulse generator circuit it may be a 555 timer IC , 556 IC, micro-processor,
micro-controller, UJT circuit, PLC or any other circuit that can able to produce
a pulse signal.
2. The output of the pulse generator circuit is supplied to the amplifier circuit and
it should be isolated from the main power circuit for protection of the
controlling circuit. The amplifier circuit may be BJT amplifier, OPAMP,
Darlington pair and so on. While the isolator circuit may be a pulse
transformer or an opto-coupler circuits.
The different methods of gate triggering are the following
R-triggering.
RC triggering.
UJT triggering
50
1. RESISTANCE TRIGGERING
v O
a b
L O A D
i R 1
R 2
v S = V m s in t
D V T
R V g
51
• The resistor R1 limits the current through the gate of the SCR.
52
V S VS VS
V m s in t
3 4 3 4 3 4
2 t 2 t 2 t
Vg Vgt Vg Vg Vgp>Vgt
Vgp= Vgt
t 0 t t
270
VT VT VT
3 4
t 2 t t
0 0
0 = 90 < 90
90
(a ) (b ) (c)
• Case 1:
Vgp , the peak gate voltage is less then Vgt since R2 is very large.
Therefore, current ‘I’ flowing through the gate is very small.
SCR will not turn on and therefore the load voltage is zero and vscr
is equal to Vs. This is because we are using only a resistive network.
Therefore, output will be in phase with input.
54
• Case 3:V gp
,
Vgt R2 small value.
The triggering value V is reached much earlier than 0. Hence the SCR
gt 90
turns on earlier than reaches its peak value. The waveforms as shown
with respect to V S .
Vs Vm sin t
At
Vgt
t , VS Vgt ,Vm Vgp Vgt Vgp sin Therefore sin 1
Vgp
Vm R
ButVgp
R1 R2 R
Vgt R1 R2 R
Therefore sin
1
V m R
vO
LOAD
+
R
D 2 VT
-
v S = V m s in t
D 1
V C C
56
• Capacitor ‘C’ in the circuit is connected to shift the phase of the gate
voltage.
• D1 is used to prevent negative voltage from reaching the gate cathode of
SCR.
• In the negative half
Vm cycle, the capacitor charges to the peak negative voltage
-/2 0 -/2 0
0 t 0 t
vc vc
vc vc
a a a a
vo vo
Vm Vm
0
t t
vT vT
Vm
0
-V m t t
-V m
(2 + )
(a ) (b )
(a) High value of R (b) Low value of R
Fig.: Waveforms for RC half-wave trigger circuit 58
OPERATION
• Case 1: R Large.
When the resistor ‘R’ is large, the time taken for the capacitance to charge
from Vm to Vgt is large, resulting in larger firing angle and lower load
voltage.
• Case 2: R Small.
When ‘R’ is set to a smaller value, the capacitor charges at a faster
rate towards Vgt resulting in early triggering of SCR and hence VL is
more.
When the SCR triggers, the voltage drop across it falls to 1 to
1.5V. This in turn lowers, the voltage across R & C.
Low voltage across the SCR during conduction period keeps the
capacitor discharge during the positive half cycle.
59
DESIGN EQUATIONS
Considering the source voltage and the gate circuit, we can write
vs I gt R VC
SCR fires when vs I gt R VC
that is vS I g R Vgt Vd 1
.
vs Vgt Vd 1
Therefore . R
I gt
The RC time constant for zero output voltage ,that is maximum firing angle
for power frequencies is empirically given as
T
RC 1.3
2
60
End of chapter one
Question?