CMOS Logic Circuit

Combinational logic circuits or gates, which perform Boolean operations on multiple

input variables and determine the outputs as Boolean functions of the inputs, are the
basic building blocks of all digital systems. In its most general form, a combinational
logic circuit, or gate, performing a Boolean function can be represented as a multiple-
input, single-output system, as depicted in the figure.

Node voltages, referenced to the ground potential, represent all input variables. Using
positive logic convention, the Boolean (or logic) value of "1" can be represented by a
high voltage of VDD, and the Boolean (or logic) value of "0" can be represented by a
low voltage of 0. The output node is loaded with a capacitance C , which represents the
L

combined capacitances of the parasitic device in the circuit.

CMOS Two Input NOR Gate

The circuit consists of a parallel-connected n-net and a series-connected

complementary p-net. The input voltages V  and V  are applied to the gates of one
X Y

nMOS and one pMOS transistor.

When either one or both inputs are high, i.e., when the n-net creates a conducting path
between the output node and the ground, the p-net is cut—off. If both input voltages
are low, i.e., the n-net is cut-off, then the p-net creates a conducting path between the
output node and the supply voltage.
The figure shows a sample layout of CMOS 2-input NOR gate, using single-layer metal
and single-layer polysilicon. The features of this layout are −

 Single vertical polylines for each input

 Single active shapes for N and P devices, respectively
 Metal buses running horizontal

CMOS Two-input NAND Gate

The circuit diagram of the two input CMOS NAND gate is given in the figure below.
The principle of operation of the circuit is exact dual of the CMOS two input NOR
operation. The n – net consisting of two series connected nMOS transistor creates a
conducting path between the output node and the ground, if both input voltages are
logic high. Both of the parallelly connected pMOS transistor in p-net will be off.
The features of this layout are as follows −

 Single polysilicon lines for inputs run vertically across both N and P active
regions.
 Single active shapes are used for building both nMOS devices and both pMOS
devices.
 Power bussing is running horizontal across top and bottom of layout.
 Output wires runs horizontal for easy connection to neighboring circuit.