INDIRA GANDHI DELHI TECHNICAL

UNIVERSITY FOR WOMEN

Lab File
VLSI DESIGN
(BEC-306)

B.Tech, Electronics and Communication Engineering- Artificial

Intelligence (2021-2025)

Submitted to : Submitted by:

Ms. Ramsha Suhail Aarti
136011802021
ECE-AI (2)
 Experiment 1
AIM: To plot output and transfer characteristics of a n-channel MOSFET.
Software Used: LTSpice
Theory: The metal–oxide–semiconductor field-effect transistor (MOSFET) is a transistor
used for amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-
insulated gate electrode can induce a conducting channel between the two other contacts
called source and drain. The channel can be of n-type or p-type, and is accordingly called
an nMOSFET or a pMOSFET.
The characteristics of an nMOS transistor can be explained as follows. As the voltage on the top
electrode increases further, electrons are attracted to the surface. At a particular voltage level, which
we will shortly define as the threshold voltage, the electron density at the surface exceeds the hole
density. At this voltage, the surface has inverted from the p-type polarity of the original substrate to
an n-type inversion layer, or inversion region, directly underneath the top plate. This inversion region
is an extremely shallow layer, existing as a charge sheet directly below the gate. In the MOS
capacitor, the high density of electrons in the inversion layer is supplied by the electron–hole
generation process within the depletion layer. The positive charge on the gate is balanced by the
combination of negative charge in the inversion layer plus negative ionic acceptor charge in the
depletion layer. The voltage at which the surface inversion layer just forms play an extremely
important role in field-effect transistors and is called the threshold voltage Vtn. The region of out.

Output:

a) Schematic Circuit
b) Output characteristic

c) Transfer Characteristics

Result: The output and transfer characteristic of NMOS are Observed.

Precautions:
1) Connections should be tight.
2) Labeling should be done right.
 Experiment 2
Aim: To plot output and transfer characteristics of p- channel MOSFET.

Software Used: LTSpice

Theory: The PMOS (P-type Metal-Oxide-Semiconductor) transistor is a fundamental building

block in semiconductor technology. Comprising a P-type semiconductor layer sandwiched between
metal and oxide layers, it plays a pivotal role in integrated circuits. The transistor's operation is
controlled by applying a positive voltage to the gate, creating a repulsive force for holes, the dominant
charge carriers in P-type semiconductors. This results in the formation of a depletion region,
facilitating the flow of current from the source to the drain.
PMOS transistors are integral components of complementary metal-oxide-semiconductor (CMOS)
technology. In CMOS, PMOS and NMOS (N-type Metal-Oxide-Semiconductor) transistors work in
tandem. While NMOS transistors handle the logical '1' state by allowing the flow of electrons, PMOS
transistors manage the logical '0' state by facilitating the movement of holes. This complementary
operation enables low-power and high-performance digital logic circuits.
The unique characteristic of PMOS transistors, with their ability to carry a positive charge,
complements the negative charge-carrying NMOS transistors. This duality contributes to the
efficiency and versatility of CMOS technology, a dominant paradigm in modern semiconductor
design, crucial for the development of advanced processors, memory devices, and other integrated
circuits in electronic systems.

Procedure:
1. Connect the MOSFET in a circuit with a variable voltage source.
2. Measure the drain current (ID) and drain-source voltage (VDS) for different values of
gate-source voltage (VGS).
3. Plot the transfer characteristics by plotting ID versus VGS for different values of VDS.
4. Plot the output characteristics by plotting ID versus VDS for different values of VGS.
5. Determine the threshold voltage (VTH) from the transfer characteristics plot, which is
the gate-source voltage at which the MOSFET just starts to conduct.
6. Determine the drain-source resistance (RDS) from the output characteristics plot, which
is the slope of the linear region of the plot.
7. Analyze the characteristics to determine the operating region of the MOSFET, which can
be either the cutoff, triode, or saturation region.

Output:
a) Schematic Diagram

Fig. 2.1 Schematic diagram

b) Output characteristics

Fig 2.2 Output Characteristics of PMOS

c) Transfer characteristics

Fig 2.3 Transfer Characteristics of PMOS

Result: The output and transfer characteristic of NMOS are Observed.

Precautions:
1) Double-check the values of the parameters in your circuit. Ensure that the values for resistor
voltage sources, and other components are set correctly.
2) Choose appropriate simulation time to capture the relevant behavior of the MOSFET.
3) The connections should be tight.
 Experiment 4
Aim: To design and plot the Dynamic Characteristics of 2-Input NAND and NOR Logic Gates
using CMOS technology.

Software Used: LTSpice

Theory: CMOS inverter : a device that is used to generate logic functions is known as CMOS
inverter and is the essential component in all integrated circuits. A CMOS inverter is aFET (field
effect transistor), composed of a metal gate that lies on top of oxygen’s insulating layer on top of a
semiconductor. These inverters are used in most electronic devices whichare accountable for
generating data in small circuits.
For the design of any circuit with the CMOS technology; We need parallel or series connections of
nMOS and pMOS with a nMOS source tied directly or indirectly to ground anda pMOS source tied
directly or indirectly to Vdd. A basic CMOS structure of any 2-input logicgate can be drawn as follows:

Fig 4.1 CMOS structure of any 2-input NAND gate and Truth table

For two input NAND gate, if A and B are the inputs then its output Y = (A.B)’
In NMOS network when we have AND operation between the two variables, then two NMOS
transistors will get connected in series. And the output will be complemented of it.
The PMOS network is dual of the NMOS network. In the NMOS network, if two transistors are
connected in series then in the PMOS network, the two PMOS transistors will get connected in
parallel.

For two input NOR gate, if A and B are the inputs then its output Y = (A+B)’
In the NMOS network, whenever there is an OR operation between the two variables then two NMOS
transistors will get connected in parallel. And the output will be complemented of it.
The PMOS network will be the dual of the NMOS network. Therefore, in the PMOS network,the two
PMOS transistors will get connected in series.
 Fig 4.2 CMOS structure of any 2-input NOR gate and Truth table

Output:

Fig 4.3 Schematic of 2-Input NAND CMOS

Fig 4.4 Input and Output of CMOS NAND gate

 Fig 4.5 Schematic of 2-Input NOR CMOS

Fig 4.6 Input and Output of CMOS NOR gate

Result: Characteristics of 2-input NAND and NOR gate using CMOS technology were plotted and
observed.

Precautions:
1. Validate the CMOS models and parameters in LTspice to accurately simulate the behavior of the
logic gates.
2. Ensure proper layout and connection of CMOS components to avoid parasitic effects that may
distort simulation results.
3. Use appropriate voltage levels and timing constraints to reflect real-world operating conditions
and prevent unrealistic simulations.
 Experiment 5
Aim: To design and plot the Dynamic Characteristics of 2-Input XOR and XNOR Logic Gates using
CMOS Technology.

Software Used: LTSpice

Theory: CMOS inverter : a device that is used to generate logic functions is known as CMOS
inverter and is the essential component in all integrated circuits. A CMOS inverter is aFET (field effect
transistor), composed of a metal gate that lies on top of oxygen’s insulating layer on top of a
semiconductor. These inverters are used in most electronic devices which are accountable for
generating data in small circuits.
For the design of any circuit with the CMOS technology; We need parallel or series connections of
nMOS and pMOS with a nMOS source tied directly or indirectly to ground anda pMOS source tied
directly or indirectly to Vdd. A basic CMOS structure of any 2-input logicgate can be drawn as follows:

Fig. 5.1 2-Input XOR circuit in CMOS Fig. 5.2 Block diagram for the XOR Gate.
 Fig. 5.3 2-Input XNOR circuit in CMOS. Fig. 5.4 Block diagram for the XNOR Gate.

Output:

Fig 5.5 Schematic of 2-Input XOR CMOS

 Fig 5.6 Input and Output of CMOS XOR gate

Fig 5.7 Schematic of 2-Input XNOR CMOS

Fig 5.8 Input and Output of CMOS XNOR gate

Result: 2-input XOR and XNOR logic gates using CMOS technology were designed and its dynamic
characteristics were plotted.
 Experiment 6
Aim: To Design and Plot the Characteristics of a 4x1 Digital Multiplexer using Pass Transistor
Logic.

Software Used: LTSpice

Theory: A multiplexer or mux is a combinational circuits that selects several analog or digital input
signals and forwards the selected input into a single output line. A multiplexer of 2n inputs has n
selected lines, are used to select which input line to send to the output.

Fig. 6.1 The schematic diagram, boolean expression and the truth table of a 4:1 multiplexer

Pass-transistor logic (PTL), also known as transmission-gate logic, is based on the use of MOSFETs
as switches rather than as inverters. The result is (in some cases) conceptual simplification, but the
CMOS inverter’s strict logic-high/logic-low output characteristic is lost.

Fig. 6.2 Symbol of Pass Transistor Logic

The pass-transistor logic attempts to reduce the number of transistors to implement a logic by allowing
the primary inputs to drive gate terminals as well as source-drain terminals. The implementation of a
2:1 MUX requires 4 transistors (including the inverter required to invert S), while a complementary
CMOS implementation would require 6 transistors. The reduced number of devices has the additional
advantage of lower capacitance
Output:

Fig. 6.3 Schematic 4x1 MUX using Pass Transistor Logic

Fig. 6.4 Input and Output of 4:1 MUX using PTL

Result: The Characteristics of a 4x1 Digital Multiplexer using Pass Transistor Logic were observed.
 Experiment 7
Aim: To Design and Plot the Characteristics of a Positive Latch based on Multiplexers.
Software Used: LTSpice
Theory: A bistable circuit- a circuit having two stable states that represent 0 and 1, can be designed
using a positive-feedback. The basic idea is shown in fig.7.1, which shows two inverters connected
in cascade along with the voltage-transfer characteristic typical of such a circuit.

Fig. 7.1 Two cascaded inverters along with their superimposed VTCs.

The above circuit has only three possible operation points (A, B, and C), as demonstrated on the
combined VTC. Out of these, A and B are the only stable operating points, and C is a metastable
point; therefore, the name bistable. The circuit serves as a memory, storing either a 1 or a 0
corresponding to positions A and B. We can change the state of such a circuit by cutting the feedback
loop or by overpowering the feedback loop. The first is called a multiplexer based Latch and it realizes
the following multiplexer equation:

A transistor-level implementation of a positive latch based on multiplexers is shown in Fig.7.2 When

the CLK is high, the bottom transmission gate is on and the latch is transparent- that is, the D input is
copied to the Q output. During this phase, the feedback loop is open, since the top transmission gate
is off.

Fig. 7.2 Positive built by using transmission gates Fig.7.3 positive latches based on multiplexers
Output:

Fig. 7.4 Schematic of positive latches on 4x1 MUX

Fig. 7.5 Input and Output waveform for Positive latches

Result: Positive latch based on multiplexers was designed and the characteristics were observed.
 Experiment 8
Aim: To Design and Plot the Characteristics of a Negative Latch based on Multiplexers.
Software Used: LTSpice
Theory: A bistable circuit- a circuit having two stable states that represent 0 and 1, can be designed
using a positive-feedback. The basic idea is shown in fig.7.1, which shows two inverters connected
in cascade along with the voltage-transfer characteristic typical of such a circuit.

Fig. 8.1 Two cascaded inverters along with their superimposed VTCs.

The above circuit has only three possible operation points (A, B, and C), as demonstrated on the
combined VTC. Out of these, A and B are the only stable operating points, and C is a metastable
point; therefore, the name bistable. The circuit serves as a memory, storing either a 1 or a 0
corresponding to positions A and B. We can change the state of such a circuit by cutting the feedback
loop or by overpowering the feedback loop. The first is called a multiplexer based Latch and it realizes
the following multiplexer equation.

Fig.8.2 shows an implementation of positive and negative static latches based on multiplexers. For a
negative latch input D is selected when the CLK is 0 whereas when the CLK is high, output is held.

Fig.8.2 Negative latches based on multiplexers

Output:

Fig. 8.3 Schematic of negative latches based on MUX

Fig. 8.4 Input and Output waveform for negative latches

Result: Negative latch based on multiplexers was designed and the characteristics were observed.