DIGITAL DESIGN

(CS /ECE/EEE/INSTR F215)

Prof. Anita Agrawal

BITS PILANI K.K. BIRLA GOA CAMPUS

 Verilog styles

 Using primitives and lower-level module instantiation

(structural style),

 Specification of output signals in terms of the input

signal transformations (dataflow style),

 Specifying algorithmically the expected behavior of

the circuit (behavior style).

9/9/2019
Anita Agrawal
 AND gate
module logic_circuit (A, B, C);
output C;
input A, B;

and G1 (C, A, B);

endmodule

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Anita Agrawal
 Example

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Anita Agrawal
 9/9/2019
Anita Agrawal
 Style Example - Structural
module half_add (X, Y, S, C);

input X,Y;
output S,C;

xor(S,X,Y);
and(C,X,Y);

endmodule

9/9/2019
Anita Agrawal
 Style Example - Instantiation
module half_add
(X,Y,S,C);

input X,Y;
output S,C;

xor(S,X,Y);
and (C,X,Y);

endmodule

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Anita Agrawal
 A N1
B S
A N2 N3
A
CO

CI

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Anita Agrawal
 Style Example - Instantiation
module full_add (A, B, CI, S, CO) ;
module half_add
(X,Y,S,C); input A, B, CI ;
output S, CO ;
input X,Y;
output S,C; wire N1, N2, N3;

half_add HA1 (A, B, N1, N2),

xor(S,X,Y); HA2 (N1, CI, S, N3);
and (C,X,Y);
or P1 (CO, N3, N2);
endmodule endmodule

9/9/2019
Anita Agrawal
 Style Example – RTL / Dataflow

module fa_rtl (A, B, CI, S, CO) ;

input A, B, CI ;
output S, CO ;

assign S = A ^ B ^ CI; //continuous assignment

assign CO = A & B | A & CI | B & CI; //continuous assignment

endmodule

9/9/2019
Anita Agrawal
 Style Example – RTL / Dataflow

module fa_rtl (A, B, CI, S, CO) ;

input A, B, CI ;
output S, CO ;

assign {CO,S} = A + B+ CI; //continuous assignment

endmodule

9/9/2019
Anita Agrawal