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(b)
6.2 (a) QA0+ = En (Ld U + Ld' QA0') + En' QA0 = En (X) + En' QA0
QA1+ = En (Ld V + Ld' (QA0 ⊕ QA1) + En' QA1 = En (Y) + En' QA1
(b)
X = Ld U + Ld' QA0'
Y = Ld V + Ld' (QA0 ⊕ QA1)
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(c) Y = Ld D3 + Ld' Si
X = Ld D2 + Ld' Q3
6.4 (a) The next state equation of Q1 can be implemented using the X function generator with the inputs
R, S, Q1, and Q2. The next state equation of Q2 can be implemented using the Y function
generator with the inputs T, Q1, and Q2. The output P can be implemented using the Z function
generator with the inputs T (C input) and the X function generator.
(b)
6.5 (a) M = S2'S1'S0'I0 + S2'S1'S0I1 + S2'S1S0'I2 + S2'S1S0I3 + S2S1'S0'I4 + S2S1'S0I5 + S2S1S0'I6 + S2S1S0I7
The 8-to-1 MUX can be decomposed into seven 2-to-1 MUXes, and implemented in four Figure
6-1(a) logic blocks.
M = S2'MX + S2MY
Mx = S1'M1 + S1M2
MY = S1’M3 + S1M4
M1 = S0'I0 + S0I1
M2 = S0'I2 + S0I3
M3 = S0'I4 + S0I5
M4 = S0'I6 + S0I7
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The X and Y functions for each block each implement one 2-to-1 mux as labeled:
(b) Three 2-to-1 MUXes (or a 4-to-1 mux) can be implemented in each Figure 6-3 logic block. In
total, three blocks are required to implement seven 2-to-1 MUXes. The X, Y, and Z function
generators for each block implement a 2-to-1 MUX as labeled:
135
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(c) Each function generator used implements a 2-to-1 mux, and has the same LUT contents:
0, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1
entity Figure6_1a is
port(X_in, Y_in: in unsigned(1 to 4);
clk, CE: in bit;
Qx, Qy: out bit;
X, Y: inout bit;
XLUT, YLUT: in unsigned(0 to 15));
end Figure6_1a;
process(clk)
begin
if clk = '1' and clk'event then
136
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if CE = '1' then
Qx <= X; Qy <= Y;
end if;
end if;
end process;
end internal;
entity LUT_Mux is
port(I0, I1, I2, I3, S0, S1: in bit;
M: out bit);
end LUT_Mux;
B0: Figure6_1a port map (in1, in2, '0', '0', open, open, M1, M2,
"0101001101010011", "0101001101010011");
B1: Figure6_1a port map (in3, "0000", '0', '0', open, open, Mout,
open,
"0101001101010011", "0000000000000000");
end internal;
entity Figure6_3 is
port(X_in, Y_in: in unsigned(1 to 4);
clk, CE, C: in bit;
Qx, Qy: out bit;
X, Y: inout bit;
XLUT, YLUT: in unsigned(0 to 15);
ZLUT: in unsigned(0 to 7);
SA, SB, SC, SD: in bit);
end Figure6_3;
137
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Z_int <= ZLUT(to_integer(Z_Index));
X <= MuxB;
Y <= MuxD;
process(clk)
begin
if clk = '1' and clk'event then
if CE = '1' then
Qx <= MuxA; Qy <= MuxC;
end if;
end if;
end process;
end internal;
entity Code_Converter is
port(X, clk: in bit;
Z: out bit);
end Code_Converter;
B0: Figure6_3 port map(input, input, clk, '1', '0', Q3, Q2, open,
open,
"0001111111000000", "0110000001000000",
"00000000", '0', '0', '0', '0');
B1: Figure6_3 port map(input, input, clk, '1', '0', Q1, open, open,
Zout,
"1010001110000000", "1010010110011000",
"00000000", '0', '0', '0', '0');
end internal;
6.8 (a) A 4-to-16 decoder requires 16 outputs, and each function needs no more than 4-variables. 8
Figure 6-1 (a) logic blocks are required.
138
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6.9 (a) 4 logic blocks are required, 8 LUT4’s (See Figure 3-6 for truth table).
a = n7 + n6 + n5 +n4
b1 = n5'n4' (n3 + n2)
b = n7 + n6 + b1
c1 = n5 + n4'n3 + n4'n2'n1
c = n7 + n6'c1
d1 = n3 + n2 + n1 + n0
d2 = n7 + n6 + n5 + n4
d = d2 + d1
(b)
X3 X2 X1(W) X0(X) F1
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
139
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6.11 (a)
6.12 (a)
140
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F1 = P′M′N+MN′+ PQN′+M′Q′N
= M′N(P′+Q′) + N′(M + PQ)
= (N + M+PQ)(N′ + M′(P′+Q′))′′
= (N + M+PQ)(N(M+PQ)) ′
6.13 (a)
6.14
141
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6.15
6.16 Expanding F around X6 results in 4 variable functions which can be realized using one function
generator each.
F = X6 (X1' X2 X3 + X2 X3' X4' + X2 X3 X4') + X6' (X2' X3' X4 + X2 X3' X4' + X3' X4 X5) + X7
F = X6 (F1) + X6' (F2) + X7
For block one: X LUT has inputs X1, X2, X3, and X4 and realizes F1 = X1' X2 X3 + X2 X3' X4' + X2 X3
X4'.
Y LUT has inputs X2, X3, X4, and X5 and realizes F2 = X2' X3' X4 + X2 X3' X4' + X3' X4 X5
For block two: X LUT has the outputs of block one’s X LUT (F1) and Y LUT (F2), X6, and X7 as
inputs. The X LUT realizes F = X6 (F1) + X6' (G1) + X7. The Y LUT is unused.
6.17 Expanding Q+ around U Q results in 4 variable equations which can be realized using one function
generator each.
For block one: X LUT has inputs V, W, X, and Y and realizes V' W + X' Y + V W'
Y LUT has inputs V, X, and Y and realizes V X' Y' + V' Y + X Y + V' X
For block two: X LUT has U, Q, and block one’s Xfunc and Yfunc as inputs and realizes
Q+ = U Q (Xfunc) + U' Q'(Yfunc)
6.18 One cell. Expanding around X5 results in 4 variable equations which can be realized using one
function generator each and X5 can be used as the C input.
X = X5 (X1' X2' X3' X4' + X1 X2 X3 X4) + X5' (X6 X7' X8' X9 + X6' X7 X8 X9')
Xfunc = (X1' X2' X3' X4' + X1 X2 X3 X4)
Yfunc = (X6 X7' X8' X9 + X6' X7 X8 X9')
Zfunc = X5 (Xfunc) + X5' (Yfunc)
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6.19 (a) Expanding Z around Y results in 4 variable equations which can be realized using one function
generator each.
Z = Y (V W' X + U' V' W) + Y' (V W' X + T V' W)
Z = Zfunc = Y (Xfunc) + Y' (Yfunc)
Implement internal logic cell connections in a manner similar to Problem 6.12 Solution with U,
V, W, and X as inputs to the X-function generator, T, V, W, and X as inputs to the Y-function
generator and Y as the C input.
Block 2: X-LUT has Y and Block 1’s Xfunc and Yfunc as inputs and realizes Z = Y (Xfunc) + Y'
(Yfunc)
Y-LUT is unused
143
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6.21 Y = e'f ' Y00 + e'f Y01 + ef ' Y10 + efY11
Y00 = 0
Y01 = abcd
Y10 = a' bc'd ' + b'c'
Y11 = ab'cd + a'bc'd'
6.22 (a) Y = a' (bc'd'e + b'c'e) + a (b'cd'e + b'c'e + bcde) = a' (Y1) + a (Y2)
Y1 = bc'd'e + b'c'e
Y2 = b'cd'e + b'c'e + bcde
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(b)
(c)
bcde Y1 (Xfunc) Y2 (Yfunc)
0000 0 0
0001 1 1
0010 0 0
0011 1 1
0100 0 0
0101 0 1
0110 0 0
0111 0 0
1000 0 0
1001 1 0
1010 0 0
1011 0 0
1100 0 0
1101 0 0
1110 0 0
1111 0 1
6.23 (a) Eight LUTs are required. Each bit of the adder requires one LUT to generate the sum and one
LUT to generate the carry-out.
(b) Four LUT4s are required. Each bit of the adder requires one LUT4 to generate the sum.
Dedicated carry chain logic generates the carry-out.
145
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(c) When Su is 1, the circuit should add a to the 2’s complement of b by inverting each bit of b and
setting bit 0’s Cin to.
Su ai bi Cin Outi
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
146
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147
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6.24 (a) 14 cells total.
(b) 14 cells total: 6 for adders and 8 for AND gates but propagation delay is less.
6.25 (a) Z = A'(BC 'D ' EF ' + B'C 'E ' F + BC ' E ' F ') + A(B'CD ' E ' F + B'C ' E ' F + BCDE)
Z = A'(Z0) + A(Z1)
Z0 = D'(Y00) + D(Y01)
Y00 = BC ' EF ' + B'C ' E ' F + BC ' E ' F
Y01 = B'C ' E ' F + BC ' E ' F '
Z1 = D'(Y10) + D(Y11)
Y10 = B'C ' E ' F + B'CE ' F
Y11 = B'C ' E ' F + BCE
148
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(b)
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6.26 F = X6 (X1' X2 X3' X4 + X2' X4' + X3 X4 X5 + X1 X3) + X6' (X2' X3' X4 + X2 X4 + X3' X4 + X1 X3)
6.27 To realize the next-state equations, we need to use at least four Kintex logic slices (Figure 6-13).
One Kintex logic slice is ¼ CLB. Therefore, only 1 CLB is needed.
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6.28
(b)
151
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(c)
(d)
6.30 The sequential circuit requires 3 Virtex slices. For the first slice, the G inputs are Q2, C, D, and E (G
= Q2' C D E). The F inputs are Q2, A, B, and C (F = Q2 A B C). The BX input is Q1. Then the X flip-
flop implements the Q1 flip-flop. Also, if the FXA input is 1, the FXB input is 0, and the BY input is
Q1, then the Y flip-flop implements Q2. For the second slice, the G inputs are Q2, A, and B (G = Q2'
A B + Q2' A' B'). The F inputs are Q2, A, B, and C (F = Q2' A B' + Q2 (A' + B + C)). The BX input is
Q1. Then the output to the F5 MUX implements Z1. For the third slice, the G inputs are Q1, Q2, A,
and B (G = Q1 A' + Q1 B + Q2'). Then the Y combinational output implements Z2.
6.31 The sequential circuit requires 2 Xilinx slices. For the first slice, D1-D5 inputs are Q1,Q2,A,B,C and
D6 is 1. O5 is read from AQ with first output. O6 is read from AMUX with second output. For the
second slice, D1-D5 takes input Q1,Q2,A,B,C. D6 is 1. O5 is read from A as Z1 and O6 is read from
AMUX combinational as Z2.
6.32 The circuit can be implemented using 2 Logic Modules. In the first LM, the common 4 inputs are
Q1,Q2,A,B. Each of the 2 inputs to the LUT's are C,0. XQ will hold Q1. This Q1 is latched onto YQ
giving Q2+. Y will hold Z1. In the second LM, only the first LUT is used with inputs Q1,A,B and
Z2 is read from X.
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6.33 The possible functions are bolded below:
i) All 32-variable functions
ii) Some 32-variable functions
iii) All 8-variable functions
iv) Some 8-variable functions
v) All 7-variable functions
vi) Some 7-variable functions
vii) All 6-variable functions
viii) Some 6-variable functions
ix) All 36-variable functions
x) Some 36-variable functions
xi) All 39-variable functions
xii) Some 39-variable functions
6.35
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6.36 (a)
entity P6_24b is
port(A: in unsigned(15 downto 0);
N: in integer range 0 to 15;
A_Shft: out unsigned(15 downto 0));
end P6_24b;
(c)
library IEEE;
use IEEE.numeric_bit.all;
entity P6_24c is
port(A: in unsigned(15 downto 0);
N: in integer range 0 to 15;
A_Shft: out unsigned(15 downto 0));
end P6_24c;
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mplier_out <= A * decoder_out;
A_shft <= mplier_out(30 downto 15);
end internal;
6.37 S0: Q0Q1Q2Q3 = 1000, S1: 0100, S2: 0010, S3: 0001
Q0+ = St'Q0 + Q3
Q1+ = StQ0 + K 'M 'Q1 + K 'Q2
Q2+ = MQ1
Q3+ = KM 'Q1 + KQ2
Load = StQ0
Done = Q3
Sh = M'Q1 + Q2
Ad = MQ1
6.38 S0: Q0Q1Q2Q3Q4Q5Q6 = 1000000, S1: 0100000, S2: 0010000, S3: 0001000, S4: 0000100, S5:
0000010,
S6: 0000001
6.39 S0: Q3Q2Q1Q0 = 0000, S1: 1100, S2: 1010, S3: 1001
To create a one-hot encoding, if Q3 is 0 in the reset state it must be 1 in all other states.
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(b) 5 Total:
1 Slice: Q0 (one LUT4 and FF), Q1 (one LUT4 and FF)
2.5 Slices: Q2: (each AND term in one half-slice, one half-slice combines 4 product terms, one
FF)
1 Slice: Q3 (one LUT4 and FF), Z1 (one LUT4)
½ Slice: Z2 (one LUT4)
6.41 To ensure proper synthesis, amend the code for Figure 4-15 as follows:
- Within the first process, ensure that all If-Then statements include an Else portion.
Figure 4-40 uses fewer resources then Figure 4-35, and each synthesis option uses about the same
amount of resources. The solution to this problem may change depending on what synthesis tool
and target device is used.
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A1 A0 B1 B0
0 0 1 1
0 1 1 0
1 0 0 1
1 1 0 1
(b)
C1 C0 D1 D0
0 0 1 1
0 1 1 0
1 0 0 0
1 1 - -
D0 = C1'C0'
D1 = C1'
(c)
157
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6.45 (a) Naïve implementation uses an 8-to-1 mux, 3 inverters (for not A), a 3-bit adder, and a 3-bit
register. The arithmetic right shift can be accomplished by feeding in C2C2C1.
An alternate implementation is possible if Co, Ad, and Sh will not become active at the same
time: use 3 tri-state buffers with tri-state controls Co, Ad, and Sh instead of the mux.
(b) The circuit is a basic ALU, with register. If Co is true, A is complemented and loaded into
register C. If Ad is true, A and B are added and loaded into C. If Sh is true, C is shifted right by
1. Sh has the highest priority, followed by Ad, and then by Co. Note that else clauses are not
used.
6.46 (a)
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6.48 (a) Unoptimized: Two 4-to-1 muxes
a1 a0 b1 b0
0 0 1 0
0 1 0 0
1 0 1 1
1 1 0 1
b 1 = a 0'
b 0 = a1
(b)
6.49
159
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6.50
6.51
6.52
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