EE529

EMBEDDED SYSTEMS
Laboratory Assignment 1

Submitted by submitted to
Aditi Gupta Dr. Shubhajit Roy Chowdhary
DD23015 SCEE
M.Tech(R) + PhD
1. Consider a 2x2 switch. It has two input data ports, x(0) and x(1), and a 2 bit
control signal ctrl. The input data are routed to output ports y(0) and y(1) according
to the ctrl signal. The function table is specified as follows:
Input Output Function
ctrl y1 y0
00 x1 x0 pass
01 x0 x1 cross
10 x0 x0 Broadcast x0
11 x1 x1 Broadcast x1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch2x2 is
Port ( x0 : in STD_LOGIC;
x1 : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC);
end switch2x2;

architecture behvl of switch2x2 is

signal ctrl : std_logic_vector(1 downto 0);
begin
process(ctrl)
begin
if (ctrl ="00") then
y1 <= x1;
y0 <= x0;
elsif(ctrl ="01") then
y1 <= x0;
y0 <= x1;
elsif(ctrl ="10") then
y1 <= x0;
y0 <= x0;
elsif(ctrl ="11") then
y1 <= x1;
y0 <= x1;
end if;
end process;
end behvl;

Code:-
x0 = 0 and x1 = 1(given input constants)

Simulation:-

2. Consider an arithmetic circuit that can perform four operations: a+b, a-b, a+1 and
a-1, where a and b are 16 bit unsigned numbers and the desired operation is
specified by a 2 bit control signal ctrl. (a) Design the circuit using two adders, one
incrementer and one decrementer. Derive the VHDL code. (b) Design the circuit
using only one adder. Derive the VHDL code. In both the cases, start with the
data-flow model of a half adder circuit. Then use the half adder as components in
your hierarchical structural design.
Solution:-
(A)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity addsub is
port (
a,b: in std_logic_vector(15 downto 0);
r: out std_logic_vector(15 downto 0);
ctrl: IN std_logic_vector(1 downto 0));
end addsub;

architecture arch of addsub is

signal temp0, temp1, sum: unsigned(15 downto 0);

begin
process(ctrl)
begin
temp0 <= unsigned(a);
temp1 <= unsigned(b);
if(ctrl="00")then
sum <= temp0 + temp1 ;
elsif (ctrl = "01")then
sum <= temp0 - temp1 ;
elsif (ctrl = "10")then
sum <= temp0 + 1 ;
elsif (ctrl = "11")then
sum <= temp0 - 1 ;
end if ;
end process;
r <= std_logic_vector(sum);
end arch;
Code:-
a= 1000010001010001; b= 0000100000000011
When ctrl =00 then a+b = 1000110001010100 ; when ctrl = 01 then a-b =
0111110001001110
When ctrl =10 then a+1 = 1000010001010010; when ctrl =11 then a-1 =
100010001010000

Simulation:-
(B)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity arithmetic_b is
Port (
a,b : in STD_LOGIC_VECTOR(15 DOWNTO 0);
ctrl : in std_logic_vector(1 downto 0);
r : out STD_LOGIC_VECTOR(15 DOWNTO 0));
end arithmetic_b;

architecture arch_b of arithmetic_b is

signal temp0, temp1 :unsigned(15 downto 0);
signal cin : unsigned(0 downto 0);
begin
temp0 <= unsigned(a);
process(ctrl)
begin
if(ctrl ="00")then
temp1 <= unsigned(b);
elsif(ctrl ="01")then
temp1 <= unsigned(not b);
elsif(ctrl ="10")then
temp1 <= "0000000000000001";
elsif(ctrl ="11")then
temp1 <= "1111111111111111" ;
end if;
end process;
cin <= "1" when ctrl ="01" else "0";
r <= std_logic_vector(temp0 + temp1 + cin);
end arch_b;
a= 1000010001010001; b= 0000100000000011
When ctrl =00 then a+b = 1000110001010100 ; when ctrl = 01 then a-b =
0111110001001110
When ctrl =10 then a+1 = 1000010001010010; when ctrl =11 then a-1 =
100010001010000

Simulation:-
3. In an analog amplifier, the output voltage becomes saturated (i.e. reaching the
most positive voltage, +Vcc or the most negative voltage, -Vcc), when the output
exceeds the maximal range. In some digital signal processing applications, we wish
to design an 8 bit signed saturation adder that mimics the behavior of an analog
amplifier; i.e. if the addition result overflows, the result becomes the most positive
or the most negative numbers. Draw the top level diagram and derive the VHDL
code accordingly.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sum_amp is
port ( a, b: in signed(7 downto 0);
sum: out signed(7 downto 0));
end sum_amp;

architecture behv of sum_amp is

signal result: signed(8 downto 0);
begin
process (a,b)
begin
result <=('0'& a) + ('0' & b);
if result > signed'("01111111") then
sum <= signed'("01111111"); -- set sum to positive maximum

elsif result < signed'("11111111") then

sum <= signed'("11111111"); -- set sum to negative minimum

else
sum <=result(7 downto 0);

end if;
end process;
end behv;
Simulation :-
a = 125, b = 25, sum = 127(positive saturation) as result = 150 exceeds upper limit

a = -125, b = -25, sum =-127(negative saturation ) as result = -150 exceeds lower limit

a = 50, b= 20, sum = 70 as result = 70 is within the the range