VHDL 4

Building blocks of a computer

VHDL 4 : (ver.0a) 1
VHDL 4
Building blocks of a computer

 We will study the building blocks of

a computer.
 Control units are state machines,
which have Flip-flops, decoders,
multiplexers etc.
 Beware that , there are usually
more than one way to design the
same digital system in VHDL

VHDL 4 : (ver.0a) 2
 A typical Control Unit
CPU State machine
 FFs=Flip-flops Registers
 A state machine (FFs)
 contains FFsAddress bus
I/O control logic
(latches) (state machine)

data-bus ALU
Transceivers (state machine)
Memory
(bi-directional
buffers )
VHDL 4 : (ver.0a) 3
 Use VHDL to make digital system
building blocks

 1) latch,
 2) flipflop with asynchronous reset,
 3) flipflop with synchronous reset,
 4) tri state buffer,
 5) decoder,
 6) multiplexer,
 7) bi-directional buffer,

VHDL 4 : (ver.0a) 4
 1) Latch: when gate=1,
output follows input (level sensitive)

 1 entity latch_ex is Latch

 2 port (gate, in1 : in std_logic;
 3 out1 : out std_logic); 1-bit memory
 4 end latch_ex; in1 D Q out1
 5 architecture latch_ex_arch of latch_ex is
gate C
 6 begin
 7 process (gate,in1)
 8 begin
 9 if (gate = '1') then
•Gated D-latch
 10 out1 <= in1; from (http://en.wikipedia.org/wiki/Latch_(electronics)

 11 end if;
 12 end process;
 13 end latch_ex_arch;
VHDL 4 : (ver.0a) 5
 Exercise 4.1 on latch: draw q
In1 Latch q
gate

in1

gate

VHDL 4 : (ver.0a) 6
2) Edge-triggered Flip-flop with asyn. reset :
reset before clock statement

 1 architecture dff_asyn_arch of dff_asyn is

 2 begin Latch
 3 process(clock, reset) with reset
 4 begin in1 D out1
 5 if (reset = '1') then
 6 out1 <= '0'; clock
 7 elsif clock = '1' and clock'event then
 8 out1 <= in1;
 9 end if;
reset
 10 end process;
 11 end dff_asyn_arch;

VHDL 4 : (ver.0a) 7
 Exercise 4.2 on flip-flops:draw ql, qe
Level Edge
D (90%) ql D (50%) qe
triggered triggered
CK CK
FF FF

CK

ql

qe
VHDL 4 : (ver.0a) 8
Exercise 4.3 on architecture dff_asyn_a
When will line 3 be executed?
Which is more powerful: clock or reset?

 1 architecture dff_asyn_arch of dff_asyn is

 2 begin
 3 process(clock, reset)
 4 begin
 5 if (reset = '1') then
 6 out1 <= '0';
 7 elsif clock = '1' and clock'event then
 8 out1 <= in1;
 9 end if;
 10 end process;
 11 end dff_asyn_arch;

VHDL 4 : (ver.0a) 9
Exercise 4.4 on different flip-flops
 What is the difference between level
triggered and edge triggered flip-flops?
 **In Xilinx-Foundation all flip-flops are
treated as 50% edge triggered flip-flops.
 What is the difference between
 synchronous reset (syn-reset) flip-flops and
 asynchronous reset (asyn-reset) flip-flops?
 Discuss the difference between a latch
and a flip flop.

VHDL 4 : (ver.0a) 10
 3) Flip-flop with syn. reset: clock before reset statement

 1 architecture dff_syn_arch of dff_syn is

 2 begin process(clock,reset) -- reset can be
removed,
 4 begin– -- but allowed
 5 if clock = '1' and clock'event then
 6 if (reset = '1') then
 7 out1 <= '0';
 8 else reset
 9 out1 <= in1; out1
 10 end if; in1 D
 11 end if;
 12 end process; clock
 13 end dff_syn_arch;

Discuss why reset is not needed in the sensitivity list

VHDL 4 : (ver.0a) 11
Difference between
Syn. & Asyn. flip-flops
 The order of the statements inside the
process determines Syn. or Asyn. reset
 if clock = '1' and clock'event then
 if (reset = '1') then

 if (reset = '1') then

 q <= '0';
 elsif clock = '1' and clock'event then

VHDL 4 : (ver.0a) 12
 4) Tri state buffer: using when-else
(Use capital letter big Z for float, Z is a reserved
character)

 1 entity tri_ex is
control
 2 port (in1, control : in std_logic;
 3 out1 : out std_logic); out1
 4 end tri_ex; in1
 5 architecture tri_ex_arch of tri_ex is
 6 begin
 7 out1 <= in1 when control = '1' else 'Z';
 8 end tri_ex_arch;

VHDL 4 : (ver.0a) 13
 A decoder (N bits --> 2N bits)


•Picture from: http://www.safesdirect.com/safes/meilink/safes.html

VHDL 4 : (ver.0a) 14
 5) Decoder: using if statements
 1 architecture decoder_a of decoder is
 2 begin
 3 process (in1, in2)
 4 begin
 5 if in1 = '0' and in2 = '0' then
 6 out00 <= '1';
 7 else out00
 8 out00 <= '0'; in1
 9 end if; out10
 10 if in1 = '0' and in2 = '1' then
 11 out01 <= '1'; out11
 12 else
 13 out01 <= '0'; in2 out01
 14 end if;
VHDL 4 : (ver.0a) 15
 (contin.)Decoder
 15 if in1 = '1' and in2 = '0' then
 16 out10 <= '1';
 17 else
 18 out10 <= '0';
 19 end if;
 20 if in1 = '1' and in2 = '1' then
 21 out11 <= '1';
 22 else
 23 out11 <= '0';
 24 end if;
 25 end process;
 26 end decoder_a;
VHDL 4 : (ver.0a) 16
 6) Multiplexer (2N bits --> N bits)
(the reverse of decoder)
 1 architecture mux_arch of mux is
 2 begin in1
 3 process (in1, in2, ctrl)
in2 out1
 4 begin
 5 if ctrl = '0' then crtl
 6 out1 <= in1;
 7 else
 8 out1 <= in2; in1 out1
 9 end if; Mux
 10 end process; end mux_arch; in2

crtl
VHDL 4 : (ver.0a) 17
7) Bi-directional bus: using data
flow concurrent statements
 1 entity inout_ex is
 2 port (io1, io2 : inout std_logic;
 3 ctrl : in std_logic); ctrl
 4 end inout_ex;
 5
 6 architecture inout_ex_a of inout_ex is
 7 --signal outbuf, inbuf : std_logic;
io2 io1
 8 begin
 9 io1 <= io2 when ctrl = '1' else 'Z';
 10 io2 <= io1 when ctrl = '0' else 'Z';
 11 end inout_ex_a;

VHDL 4 : (ver.0a) 18
Exercise 4.5 for Bi-directional bus
 Crt=1, “io1” follow “io2_in”
 Crt=0, “io2” follow “io1_in” ctrl
 Plot io1 io2
io2 io1
Io2_in Io1_in
R=10K R=10K

ctrl

Io1_in
io1

Io2_in
Io2
VHDL 4 : (ver.0a) 19
Quick revision
 You should know how to design
 asynchronous , synchronous reset flip-
flops
 tri state buffers,
 Combination logics
 decoders,
 multiplexers,

 bi-directional buffers,

VHDL 4 : (ver.0a) 20
 Appendix: do variables in processes have memory.
(Good practice: Initialize variables before use; assign values to
variables from input first)
 library IEEE;
 use IEEE.std_logic_1164.all;
 entity test is port (a,reset_v1: in std_logic;
 b ,c: out std_logic); end test;
 architecture test_arch of test is
 begin
 label_proc1: process (a,reset_v1)
 variable v1 : std_logic;
 begin
 if reset_v1 ='1' then
 v1:= not a;
 end if;
 b<=a;
 c<=v1;
 end process label_proc1;
 end test_arch;
•V1 stays at two different levels depending on previous result
 **The answer is yes. That means after a process is called, the state of a variable will be
stored for the next time the process is being run again.

VHDL 4 : (ver.0a) 21