Department of Electrical Engineering

Faculty Member: Arooj Nawaz Dated: 24-March, 2021

Course/Section: BEE-10B Semester: Spring 2021

EE-351 Digital System Design

Lab 3
PLO 4 PLO5 PLO8 PLO9

Name Reg. No Viva / Analysis Modern Ethics Individua Total

Quiz / of data Tool and l and
Lab in Lab Usage Safety Team
Performa Report Work
nce

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

Maryam Mahmood 257913

Ayesha Zahid 246626

Objective
The main objective of this lab is to:

 to combinational circuits that can perform binary-to-decimal number conversion

 to design binary-coded-decimal (BCD) addition.
 to display the numbers on seven segment display
 to design full adder circuit
 to convert a BCD number to decimal number using 2 different approaches. One is
using assignment operator and second by using if-else statements.

Introduction

This lab is based on the simple concepts of using assignment operator for performing
multiple tasks. In this lab we will learn how to design combinational circuits to
perform binary to decimal number conversion. Moreover, we will learn to design
binary-coded-decimal (BCD) addition, to display the numbers on seven segment
display, to design full adder circuit, to convert a BCD number to decimal number using
2 different approaches. One is using assignment operator and second by using if-else
statements.
This lab will help us to strengthen the basic concepts of using Quartus and Verilog
hardware design language.
Task 1

Module
 Timing Diagram

Test bench Module

 RTL Viewer

Truth Tables

Circuit A

Inputs Outputs

V[3] V[2] V[1] V[0] X[3] X[2] X[1] X[0]

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 1

1 1 0 0 0 0 1 0

1 1 0 1 0 0 1 1

1 1 1 0 0 1 0 0

1 1 1 1 0 1 0 1

X[0] = V[0];
Boolean X[1] = ~V[1];
Expressions X[2] = V[1]&V[2];
X[3] = 0;
 Comparator

Inputs Outputs
V[3] V[2] V[1] V[0] z
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Boolean Expression z = (V[3]&V[2]) | (V[3]&V[1])

MUX

s M
0 S0
1 S1

Boolean Expression M = (~s & S0) | (s & S1])

 Decoder

Inputs Outputs
V[3] V[2] V[1] V[0] H[6] H[5] H[4] H[3] H[2] H[1] H[0]
0 0 0 0 1 0 0 0 0 0 0
0 0 0 1 1 1 1 1 0 0 1
0 0 1 0 0 1 0 0 1 0 0
0 0 1 1 0 1 1 0 0 0 0
0 1 0 0 0 0 1 1 0 0 1
0 1 0 1 0 0 1 0 0 1 0
0 1 1 0 0 0 0 0 0 1 0
0 1 1 1 1 1 1 1 0 0 0
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 1 1 0 0 0

H[0] = (V[2]&~V[1]&~V[0]) | (~V[3]&~V[2]&~V[1]&V[0]);

H[1] = (V[2]&~V[1]&V[0]) | (V[2]&V[1]&~V[0]);
H[2] = (~V[2]&V[1]&~V[0]);
Boolean Expression H[3] = (~V[2]&~V[1]&V[0]) | (V[2]&~V[1]&~V[0]) | (V[2]&V[1]&V[0]);
H[4] = (V[0]) | (V[2]&~V[1]);
H[5] = (~V[2]&V[1]) | (V[1]&V[0]) | (~V[3]&~V[2]&V[0]);
H[6] = (V[2]&V[1]&V[0]) | (V[3]&~V[2]&~V[1]);
Task 2

Module
Test bench Module

RTL Viewer
Timing Diagram
Task 3

Module
 Timing Diagram

S
Test bench Module

RTL viewer
Task 4

Module
Test Bench Module
Timing Diagram

RTL Viewer
Conclusion
In this lab we strengthen our concepts of building Quartus projects. This lab helped us learn
building Quartus projects using assignment operator. In this lab, we have learned how to
design combinational circuits that can perform binary-to-decimal number conversion, we have
successfully designed binary-coded-decimal (BCD) adder and displayed them on seven
segment display. We successfully implemented the design of full adder circuit. We wrote a
program in Verilog hardware language to convert a BCD number to decimal number using 2
different approaches. One is using assignment operator and second by using if-else statements.