Project

KHULNA UNIVERSITY OF ENGINEERING AND TECHNOLOGY
Department of Electronics & Communication Engineering
Course Name:
Course No:
projrct name:
to
 Objectives:
1.To analyze the given function.
2.To simplify the given function and make logic circuit
for that.
3.To learn how to write down three separate Verilog
design programs for the simplified Boolean expression in
gate level, data flow level, and behavioral level modeling.
Introduction:
In this project, we will be analyzing a Boolean function,
F(a,b,c,d,f), using the product of sums(POS)form. The
POS form is one of the two canonical forms of Boolean
algebra, the other being the sum-of-products(SOP)form.
The given Boolean function takes 5 boolean inputs
a,b,c,d,f and produces a single Boolean output. The
function has a total of 32 possible input combinations and
produces a unique output for each combination. We will
first convert the function to the POS form and then use
Karnaugh maps to simplify it. The function is widely used
in cryptography and network security.
 Theory:
The sum of all literals, either with complement or without
complement, is known as a maxterm. They are expressed
in product of sum (POS) canonical form. The value
correspond to 0 or false is selected as maxterm.
The function we are given is,
F(a,b,c,d,f)=ℿ(1,4,9,14,22,28,30)
Using the maxterms provided,we can write the POS form
of the function as follows:
F(a,b,c,d,f)=(a+c+d+gꞋ) (b’+c’+d’+g) (a’+c’+d’+g)

(a’+b’+c’+g) (a+b+c’+d+g)
We can simplify the function by using k-map. The k-map

for F(a,b,c,d,f) is shown below:
000 c’+d’+g
g c+d+g’ c+d’+g’ c+d’+g 001 c’+d’+g’
011 c’+d+g’
010 110
c’+d+g 111 101 100
00
a+b 0 0
a+b’
01 0 0
a’+b’
11 0 0
a’+b
10 0
Groups
(1,9) a+c+d+g’
(14,30) b’+c’+d’+g
(22,30) a’+c’+d’+g’
(28,30) a’+b’+c’+g
(4) a+b+c’+d+g
The simplified equation, y= ( a+c+d+g’) (b’+c’+d’+g)

(a’+c’+d’+g) (a’+b’+c’+g) (a+b+c’+d+g)
Truth table:
a b c d g y
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 1
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 1 1
0 0 1 1 0 1
0 0 1 1 1 1
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 0 1 1 1
0 1 1 0 0 1
0 1 1 0 1 1
0 1 1 1 0 0
0 1 1 1 1 1
1 0 0 0 0 1
1 0 0 0 1 1
1 0 0 1 0 1
1 0 0 1 1 1
1 0 1 0 0 1
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 1 1
1 1 0 0 0 1
1 1 0 0 1 1
1 1 0 1 0 1
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 1 1
 Programs:
Data flow level model:

//code your design here
module max(input A, input B, input C, input D, input G, output X);
assign A1=~A;
assign B1=~B;
assign C1=~C;
assign D1=~D;
assign G1=~G;
assign X=(A|C|D|G1)&(C1|B1|D1|G)&(A1|C1|D1|G)&(A1|B1|C1|G)&(A|B|
C1|D|G);
endmodule
Behavioual level model:
module max(A,B,C,D,G,X);
input A,B,C,D,G;
output X;
wire A,B,C,D,G;
reg X;
always@(A,B,C,D,G)
begin
case({A,B,C,D,G})
5'b00001:X=0;
5'b00100:X=0;
5'b01001:X=0;
5'b01110:X=0;
5'b10110:X=0;
5'b1100:X=0;
5'b11110:X=0;
default:X=1;
endcase
end
endmodule
Gate level model:
module max(A,B,C,D,G,X); //start of the module body input A,B,C,D,G;

//declaring input ports
output X; //declaring output ports

wire A1,B1,C1,D1,G1,o1,o2,o3,o4,o5; //instantiations of the module gate_level
not (A1,A); //assigning required gate
not (B1,B); //assigning required gate
not (C1,C); //assigning required gate
not (D1,D); //assigning required gate
not (G1,G); //assigning required gate
or (o1,A,C,D,G1); //assigning required gate
or (o2,B1,C1,D1,G1); //assigning required gate
or (o3,A1,C1,D1,G); //assigning required gate
or (o4,A,B,C1,D,G);
and (X,o1,o2,o3,o4); //assigning required gate
endmodule //end of the module
Test-bench:
// Code your testbench here
// or browse Examples
module testbench();
reg a,b,c,d,g;//input declared as reg the store values during simulation.
wire x;//output declared as wire as they don't store values during simulation
max f1(a,b,c,d,g,x);
initial
begin
a = 0; b = 0; c = 0; d = 0; g=0;//initialize inputs
#10;//adding 10 units of time before executing the statement
$display("\tA=%b\tB=%b\tC=%b\tD=%b\tG=%b\t=\tX=%b\t",a,b,c,d,g,x);
a = 0; b = 0; c = 0; d = 0; g=1;
#10;
a = 0; b = 0; c = 0; d = 1; g=0;
#10;
a = 0; b = 0; c = 0; d = 1; g=1;
#10;
a = 0; b = 0; c = 1; d = 0; g=0;
#10;
a = 0; b = 0; c = 1; d = 0; g=1;
#10;
a = 0; b = 0; c = 1; d = 1; g=0;
#10;
a = 0; b = 0; c = 1; d = 1; g=1;
#10;
a = 0; b = 1; c = 0; d = 0; g=0;
#10;
a = 0; b = 1; c = 0; d = 0; g=1;
#10;
a = 0; b = 1; c = 0; d = 1; g=0;
#10;
a = 0; b = 1; c = 0; d = 1; g=1;
#10;
a = 0; b = 1; c = 1; d = 0; g=0;
#10;
a = 0; b = 1; c = 1; d = 0; g=1;
#10;
a = 0; b = 1; c = 1; d = 1; g=0;
#10;
a = 0; b = 1; c = 1; d = 1; g=1;
#10;
a = 1; b = 0; c = 0; d = 0; g=0;
#10;
a = 1; b = 0; c = 0; d = 0; g=1;
#10;
a = 1; b = 0; c = 0; d = 1; g=0;
#10;
a = 1; b = 0; c = 0; d = 1; g=1;
#10;
a = 1; b = 0; c = 1; d = 0; g=0;
#10;
a = 1; b = 0; c = 1; d = 0; g=1;
#10;
a = 1; b = 0; c = 1; d = 1; g=0;
#10;
a = 1; b = 0; c = 1; d = 1; g=1;
#10;
a = 1; b = 1; c = 0; d = 0; g=0;
#10;
a = 1; b = 1; c = 0; d = 0; g=1;
#10;
a = 1; b = 1; c = 0; d = 1; g=0;
#10;
a = 1; b = 1; c = 0; d = 1; g=1;
#10;
a = 1; b = 1; c = 1; d = 0; g=0;
#10;
a = 1; b = 1; c = 1; d = 0; g=1;
#10;
a = 1; b = 1; c = 1; d = 1; g=0;
#10;
a = 1; b = 1; c = 1; d = 1; g=1;
#10;
#10;
end
initial
begin
$dumpfile("dump.vcd");// create a file that contains the dumped waveforms
$dumpvars(1);//define the scope of the dump.
end
endmodule
Result analysis:
After simplifying the given function, the Verilog code

was established and run in EDA playground with the
designed test-bench. Before running the code ,I selected
“Aldec Rivera pro 2022.04” as tools and for simulations
the option “open EPwave after run” was choosen. I
designed three separate Verilog programs: data flow level,
gate level and behavioural modeling and wrote test bench
for these respectively.
After executing the programs, we got agreeing truth table
that was designed for the program. For example, it was
depicted that if the inputs of a,b,c,d,g are zero the output
F will be 1. Another example,if a,b,c,d,f are all 1,then the
output is 1.
In timing diagram the horizontal line represents 0 and
vertical line represents 1.There were 5 lines signifying 5
inputs(a,b,c,d,g) and one line represents output F.The
value of 0 is depicted in blue ink and the value of 1 is
depicted in green ink.
Discussion:
For designing the programs a module named max was declared where all the
inputs and output were called. From here all the programs were produced
according to syntax of Verilog programme.
At first we started designing data flow level.All the inputs (a,b,c,d,g) and output X
was declared there. And our simplified expression was assigned to output X. In
code, bar sign signifies ‘~’ , + signifies ‘|’ ans * sign signifies ‘&’. Then the module
was ended with ‘endmodule’ statement.
Then behavioural modeling was designed. For behavioral programs, reg means
the output and wire is equivalent to inputs. In behavioral model, the statements
inside the always block will be executed whenever the variables in the
parenthesis after the @ symbol changes. Here in 5’b00000:F=0 means for this 5
bit wide configuration of input which are equivalent to a,b,c,d and g respectively,
the output (f) will come 0. Similarly for 5’b00001, 5’b00000, 5’b00111 etc. when
all of these conditions are not fulfilled then will go to the default statement where
f=1. Here multiple statements are declared between begin and end statement. In
test-bench, $dumpfile("dump.vcd"); $dumpvars(1) these two lines are needed so
that the code can run on EDA playground and wave is generated. Here in #10
means each configuration will change after every 10ns. $display() statement
shows the result of output for each configuration in the console.
In gate level model,the inputs that goes through different gates according to the
model are specified along with the input. For example not (A1,A) means that A1=
A’, or(o1,A,C,D,G1) means o1=A+C+D+G1, and(X,o1,o2,o3,o4) means
X=o1×o2×o3×𝑜4
Conclusion:
In this project,the given Boolean function was analyzied using the POS form. The
function was converted to the POS form and then simplified it using k-map. From
that expression three types of Verilog codes and test-bench were written and run
through the software EDA playground that gave us timing diagram and program
execution details in the log. This time diagram and console satisfies the same
truth-table that were prepared earlier. So, In conclusion,it can be said that the
implementation of the F(a,b,c,d,f)=Π(1,4,9,14,22,28,30) function using Verilog
HDL was successful and all the objectives of this project were fulfilled completely.

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KHULNA UNIVERSITY OF ENGINEERING AND TECHNOLOGY

Department of Electronics & Communication Engineering

F(a,b,c,d,f)=(a+c+d+gꞋ) (b’+c’+d’+g) (a’+c’+d’+g)

We can simplify the function by using k-map. The k-map

The simplified equation, y= ( a+c+d+g’) (b’+c’+d’+g)

Data flow level model:

module max(input A, input B, input C, input D, input G, output X);

Behavioual level model:

Gate level model:

module max(A,B,C,D,G,X); //start of the module body input A,B,C,D,G;

output X; //declaring output ports

not (A1,A); //assigning required gate

not (B1,B); //assigning required gate

not (C1,C); //assigning required gate

not (D1,D); //assigning required gate

not (G1,G); //assigning required gate

or (o1,A,C,D,G1); //assigning required gate

or (o2,B1,C1,D1,G1); //assigning required gate

or (o3,A1,C1,D1,G); //assigning required gate

and (X,o1,o2,o3,o4); //assigning required gate

endmodule //end of the module

// Code your testbench here

reg a,b,c,d,g;//input declared as reg the store values during simulation.

#10;//adding 10 units of time before executing the statement

$dumpfile("dump.vcd");// create a file that contains the dumped waveforms

$dumpvars(1);//define the scope of the dump.

After simplifying the given function, the Verilog code

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