LAB-1(Individual)

Implementation of Half Adder

and Full Adder at three
abstraction level Coding

Engineer. Ali Sabir

Prof. Rashad M. Ramzan
Dr. Hassan Saif

Electrical Engineering Department

National University of Computer &
Emerging Sciences (FAST-NU)
Islamabad-44000, Pakistan

11/10/2021 VLSI Lab 1

1.1 AIM
The purpose of this lab is to introduce you to the basic programming tools. For the purposes of this lab you
will implement an half adder and full adder circuit using VLSI design flow.

1.2 OBJECTIVE
• Verify that the Xilinx tools are up and running
• Introduce you to the Xilinx ISE software.
• Become familiar with Verilog coding and use of the ISE simulator.
• Be able to synthesize and implement Verilog designs using ISE..
1.3 THEORY

1.3.1 INTRODUCTION.
This is a step-by-step tutorial for building a 1-bit full adder in Xilinx ISE 8.2, a Design Suite software that
provides designers with the ability to code designs in a hardware description language such as VHDL or
Verilog. The ISE Design Suite also provides the ability to apply FPGA pin and timing constraints, analyze
for errors and violations, and synthesize to generate configuration bit file formats for FPGAs.

By the end of this tutorial, a student should be able to:

• Create a new design by VHDL coding.

• Verify the function of a design by behavioral simulation.
• Map a design on device through placement and routing procedures.
• Estimate the performance of the design by timing analysis
1.3.2 HALF ADDER
An adder is a digital logic circuit in electronics that implements addition of numbers. In many computers
and other types of processors, adders are used to calculate addresses, similar operations and table indices
in the ALU and also in other parts of the processors. These can be built for many numerical representations
like excess-3 or binary coded decimal. Adders are classified into two types: half adder and full adder. The
half adder circuit has two inputs: A and B, which add two input digits and generate a carry and sum.

By using half adder, you can design simple addition with the help of logic gates.Let’s see an addition of
single bits.

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HALF ADDER TRUTH TABLE

INPUT OUTPUT

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Table 1.1 Half Adder truth table
Now it has been cleared that 1-bit adder can be easily implemented with the help of the XOR Gate for the
output ‘SUM’ and an AND Gate for the ‘Carry’. When we need to add, two 8-bit bytes together, we can be
done with the help of a full-adder logic. The half-adder is useful when you want to add one binary digit
quantities. A way to develop a two-binary digit adders would be to make a truth table and reduce it. When
you want to make a three binary digit adder, do it again. When you decide to make a four digit adder, do it
again. The circuits would be fast, but development time is slow.

CIRCUIT DIAGRAM

Fig 1.1 Half Adder Logic Circuit

1.4 Verilog Code for Half Adder

1.4.1 Data Flow Modeling
module halfadder (a,b,sum,carry)
input a;
input b;
output sum;
output carry;
assign sum=a ^ b ;
assign carry=a & b; endmodule

11/10/2021 VLSI Lab 1

1.4.2 Test Bench
module halfadder_tb();
// Inputs
reg a;
reg b;
//outputs
wire sum;
wire carry;

// Instantiate the Unit Under Test (UUT)

halfadder uut(.a(a), .b(b), .sum(sum), .carry(carry));

initial begin
a=0;
b=0;
#100
a=0;
b=1;
#100
a=0;
b=1;
#100
a=1;
b=0;
#100
a=1;
b=1;
end
endmodule

1.4.3 Structural Modeling

module halfadder (a, b, s, c);
input a, b;
output s, c;
xor (s, b, a);
and (c, b, a);
endmodule

1.4.2 Behavioural Modeling

module halfadder3(a, sum, carry);
input [1:0] a;
output reg sum,carry;
always@(a)
begin

case(a)
2'b00:
begin
sum <= 0;
carry <= 0;

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 end
2'b11:
begin
sum <= 0;
carry <= 1;
end
default:
begin
sum <= 1;
carry <= 0;
end
endcase

end
endmodule
1.4.3 Test Bench
module halfadder_tb();
// Inputs
reg [1:0] a;
//outputs
wire sum;
wire carry;

// Instantiate the Unit Under Test (UUT)

halfadder uut(.a(a), .b(b), .sum(sum), .carry(carry));

initial begin
a=0;
#100
a=1;
#100
a=2;
#100
a=3;
end
endmodule

1.5 Full Adder

This adder is different to implement than a half adder. The difference between a half adder and full adder
is that the full adder has three inputs and two outputs wheres half adder has only two inputs and two output.
The first two inputs are A and B the third input is an input carry as C-IN, when a full adder logic is designed
you string eight of them togather to create a byte-wider adder and cascade the carry bit from one adder to
the next.

11/10/2021 VLSI Lab 1

1.5.1 Truth Table

INPUT OUTPUT
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1

1 0 1 1 0
1 1 0 1 0

1 1 1 1 1
Table 1.2 Half Adder truth table

1.5.2 Circuit Diagram

Fig 1.1 Full Adder Logic Circuit

1.6 Verilog Code for Half Adder

1.6.1 Data Flow Modeling
module fulladder(a_in, b_in, c_in, sum, carry);
input a_in, b_in,c_in;
output sum, carry;
assign sum = a_in^b_in^c_in;
assign carry = (a_in & b_in)|(b_in & c_in)|(a_in & c_in);

endmodule

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1.6.2 Test Bench
module FA();
reg a_in;
reg b_in;
reg c_in;

// Outputs
wire sum;
wire carry;

// Instantiation
fulladder uut(.a_in(a_in), .b_in(b_in), .c_in(c_in), .sum(sum),
.carry(carry)
);
initial begin
a_in=0;
b_in=0;
c_in=0;
#100
a_in=0;
b_in=0;
c_in=1;
#100
a_in=0;
b_in=1;
c_in=0;
#100
a_in=0;
b_in=1;
c_in=1;
#100
a_in=1;
b_in=0;
c_in=0;
#100
#100
a_in=1;
b_in=0;
c_in=1;
#100
a_in=1;
b_in=1;
c_in=0;
#100
a_in=1;
b_in=1;
c_in=1;
end
endmodule

11/10/2021 VLSI Lab 1

1.6.3 Behavioural Modeling
module fulladder(abc, sum, carry);
input [2:0] abc;
output sum,carry;
reg sum,carry;
always@(abc)
begin
{c_out, sum} = abc[0] + abc[1] + abc[2];
end
endmodule
1.6.3 Test Bench
module FA();
reg [2:0] abc;

// Outputs
wire sum;
wire carry;

// Instantiation
fulladder uut(.abc(abc), .sum(sum), .carry(carry)
);

initial begin
abc=0;
#100
abc=1;
#100
abc=2;
#100
abc=3;
#100
abc=4;
#100
abc=5;
#100

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 abc=6;
#100
abc=7;
end
endmodule

1.7 IN LAB-TASK
Implement 4-bit full adder at gate level also create their test bench.

1.8 POST LAB TASK

Implement the encoder at data flow and behavioural level modeling.
ENCODER:

A 2^n-to-n encoder has n number of outputs in correspondence to the 2^n number of inputs. It thus
reduces the number of transmission lines and can be compared to a multiplexer. Only one of the
inputs become "high" (logic state "1") at a time.
Example:
• 8:3 encoder ( you are required to implement 8:3 encoder)

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1.8.1 Data Flow Modeling

1.8.2 Test Bench

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1.8.3 Behavioural Modeling

1.8.4 Test Bench

11/10/2021 VLSI Lab 1