Digital Electronics 1 ET1003

SINGAPORE POLYTECHNIC

School of Electrical & Electronic Engineering

Name: LOH JIA HUNG

Admission No: 1901003

SAS code:

CLASS: DARE/FT/1B/22
LAB1

Lab Assignment Set No: 2_

Task : To design an Octal-to-7-segment decoder for a common cathode display

using basic logic gates (i.e. AND, OR and NOT) and ………….

Requirements:

 Decoder driver outputs are assumed

 A logic High output is required ……………….
 A truth-table comprising 3 input columns for the 3-input variables of C B A
and 7 output columns for outputs a, b, c, d, e, f, and g is required.
 Logic simplification is done using……………….
 Don’t care states are assumed for the following digits………………………..
 Etc………….
NB: Note that this is just a sample template for the report. Change or Modify as
necessary or use a different template if you prefer.
If you are using this template, complete and fill in the blanks as specified in
the dotted lines…… and add any additional requirements as necessary.

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Note

The digits required for the 7-segment display are as shown:

…………………………..

 The required Truth-table is as listed:

Decoder Inputs Decoder Outputs

C B A a b c d e f g

0 0 0 1 1 1 1 1 1 0

0 0 1 0 1 1 0 0 0 0

0 1 0 1 1 0 1 1 0 1

0 1 1 1 1 1 1 0 0 1

1 0 0 0 1 1 0 0 1 1

1 0 1 1 0 1 1 0 1 1

1 1 0 1 0 1 1 1 1 1

1 1 1 1 1 1 0 0 0 0

There are 3 input variables C B A leading to eight combinations with 2 combinations

being don’t care conditions since they do not exists. Mark these don’t care conditions
as ‘X’s.

As there are 7 outputs, there will be 7 Boolean equations for the decoder. These
decoder expressions may be simplified through the use of K-maps or through the use
of Boolean theorems. K-maps should preferably be used as it allows you to take
advantage of don’t care conditions which would not be so apparent if you use
Boolean theorems.

Also check and see if there are any similar output columns. If there are then it means
the outputs share the change expression or circuit.

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Logic Expressions Simplification

 Decoder output ‘a’

Eg Kmap working, Boolean expression, gates implementation, etc

A BA B

1 X X 1

C X 1 1 1

a=1

 Decoder output ‘b’

A BA B

1 X X 1

C X 0 1 0

b=A' + BC

 Decoder output ‘c’

A BA B

1 X X 0

C X 1 1 1

c=B' + A

 Decoder output ‘d’

A BA B

1 X X 1

C X 1 0 1

d=B' + C'

 Decoder output ‘e’

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A BA B

1 X X 1

C X 0 0 1

e=C'

 Decoder output ‘f’

A BA B

1 X X 0

C X 1 0 1

f=B' + AC'

 Decoder output ‘g’

A BA B

0 X X 1

C x 1 0 1

f=BC' + B'C

 Implementation using NAND gates …….

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Important
You must include the following declaration in your Report:
I declare that this submission does not contain plagiarised content.

Signature: _____________________