Combinational Logic

Objectives

• Types of Logic Circuits

• Combinational
• Sequential
• Designing Combinational Circuits
• Procedure
• Examples
 Combinational Circuits

• Two classes of logic circuits:

• Combinational Circuits
• Sequential Circuits
• A Combinational circuit consists of logic gates
• Output depends only on input
• A Sequential circuit consists of logic gates
and memory
• Output depends on current inputs and previous ones
(stored in memory)
• Memory defines the state of the circuit.
 Combinational Circuits

n inputs Combinational
m outputs
Circuits

A combinational circuit has:

• n Boolean inputs (1 or more),
• m Boolean outputs (1 or more)
• logic gates mapping the inputs to the outputs
 Designing Combinational Circuits

• How to design a combinational circuit?

• Use all the information and tools you learned

• Binary system, Boolean Algebra, K-Maps, etc.
• Follow the step-by-step procedure given next
 Design Procedure

1. Specification
• Write a specification for the circuit if one is not already
available
• Specify/Label input and output
2. Formulation
• Derive a truth table or initial Boolean equations that define
the required relationships between the inputs and outputs,
if not in the specification
• Apply hierarchical design if appropriate
3. Optimization
• Apply 2-level and multiple-level optimization (Boolean
Algebra, K-Map, software)
• Draw a logic diagram or provide a netlist for the resulting
circuit using ANDs, ORs, and inverters
 Design Procedure (Cont.)

4. Technology Mapping
• Map the logic diagram or netlist to the implementation
technology selected (e.g. map into NANDs)
5. Verification
• Verify the correctness of the final design manually or
using simulation

Practical Considerations:
• Cost of gates (Number)
• Maximum allowed delay
• Fanin/Fanout
 Practical Considerations

• Cost of gates (Number)

• Maximum allowed delay
• Fanin/Fanout
 Example 1

Question: Design a circuit that has a 3-bit input and a single

output (F) specified as follows:
- F = 0, when the input is less than (5)10
- F = 1, when the input is greater than (5)10
Solution: Step 1: Label the inputs (3 bits) as X, Y, Z
X is the most significant bit, Z is the least significant bit
The output of the circuit is high when input is greater
than (101)2. Therefore, output will be logic 1 for the
input combinations: (101)2, (110)2, (111)2
The output will be logic 0 for the other inputs
 Example 1 (cont.)

Step 2 (Formulation) Step 3 (Optimization)

Obtain Truth table YZ
X 00 01 11 10
X Y Z F 0 0 0 0 0 F = XZ + XY
0 0 0 0
1 0 1 1 1
0 0 1 0
0 1 0 0 Circuit Diagram
0 1 1 0 X

1 0 0 0 Z
F
1 0 1 1 X
Y
1 1 0 1
1 1 1 1
 Example 2 : Code Converters

• Code converters convert from one code to another.

e.g. BCD to Excess-3 code
• The inputs are defined by the code that is to be
converted BCD for this example (How long is the
input?)
• The outputs are defined by the converted code.
Excess-3 for this example
• Design a BCD-to-Excess-3 Code Converter.
• Excess-3 code is a decimal digit plus three
converted into binary. 0 is 0011, 1 is 0100, etc.
Example 2: BCD to Excess-3 Converter
(Formulation/Truth Table)

BCD Input Excess 3 Output

Decimal A B C D W X Y Z
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
10-15 All other inputs X X X X
 Example 2 (cont.)

BCD Input Excess 3 Output

Step 1 (Specification)
Decimal A B C D W X Y Z
• 4-bit BCD input
0 0 0 0 0 0 0 1 1
(A,B,C,D)
1 0 0 0 1 0 1 0 0
• 4-bit E-3 output
(W,X,Y,Z) 2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
Step 2 (Formulation) 5 0 1 0 1 1 0 0 0
Obtain Truth table 6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
10-15 All other inputs x x x x
 Example 2: BCD to Excess-3 Converter
(Optimization)

CD CD
AB 00 01 11 10 AB 00 01 11 10
00 0 0 0 0 00 0 1 1 1
01 0 1 1 1 01 1 0 0 0
11 X X X X X X X X
11
10 1 1 X X 0 1 X X
10
W = A + BC + BD X = B’C + BC’D’+B’D
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 1 0 1 0 00 1 0 0 1
01 1 0 1 0 01 1 0 0 1
11 X X X X X X X X
11
10 1 0 X X 1 0 X X
10
Y = CD + C’D’ Z = D’
 Example 2: BCD to Excess-3 Converter (Circuit)

W = A + BC + BD
X = B’C + BC’D’+B’D
Y = CD + C’D’
Z = D’
 Example 3: BCD to 7 Segment Display Controller
(Description)

• This display controller is

used in devices such as
digital watches to display
digits
• Each digit consists of 7
segments (C0, C1,…C6)
Example: 7 is
• The segments are Light displayed by setting
C0=C1=C2 = 1
Emitting Diodes (LEDs), C0
which light up whenever C1
C5
the value of the segment
C6
is 1, and are off when the C4 C2
value of the segment is 0
C3
 Example 3: BCD to 7 Segment Display Controller
(Specification)

• Step 1: Specify the inputs and the

outputs for the circuit
• 4 inputs (A, B, C, D)
• 7 outputs (c0, c1, c2, c3, c4, c5, c6)
• Invalid inputs (BCD greater than 1001)
will turn off all display LEDs (all zeroes)
 Example 3: BCD to 7 Segment Display Controller
(Formulation / Truth Table)

BCD INPUT 7 SEGMENT OUTPUT

Decimal A B C D C0 C1 C2 C3 C4 C5 C6
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1
10-15 All Other Inputs 0 0 0 0 0 0 0
 Example 3: BCD to 7 Segment Display Controller
(Optimization)

CD CD
AB 00 01 11 10 AB 00 01 11 10
00 1 0 1 1 00 1 1 1 1
01 0 1 1 1 01 1 0 1 0
11 0 0 0 0 11 0 0 0 0
10 1 1 0 0 10 1 1 0 0
C0 = A’C + A’BD + AB’C’ + B’C’D’ C1 = A’B’ + A’C’D’ + A’CD + B’C’
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 1 1 1 0 00 1 0 1 1
01 1 1 1 1 01 0 1 0 1
11 0 0 0 0 11 0 0 0 0
10 1 1 0 0 10 1 0 0 0
C2 = A’B + B’C’ + A’C’ + A’D
C3 =A’CD’ + A’B’C + B’C’D’+A’BC’D
 Example 3: BCD to 7 Segment Display Controller
(Optimization)
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 1 0 0 1 00 1 0 0 0
01 0 0 0 1 01 1 1 0 1
11 0 0 0 0 0 0 0 0
11
10 1 0 0 0 1 1 0 0
10
C4 = A’CD’ + B’C’D’ C5 = A’BC’ + A’C’D’ + A’BD’ + AB’C’

CD
AB 00 01 11 10
00 0 0 1 1
01 1 1 0 1
11 0 0 0 0
10 1 1 0 0
C6 = A’CD’ + A’B’C + A’BC’ + AB’C’
 Example 3: BCD to 7 Segment Display Controller
(Optimization)

C0 = A’C + A’BD + AB’C’ + B’C’D’

C1 = A’B’ + A’C’D’ + A’CD + B’C’
C2 = A’B + B’C’ + A’C’ + A’D
C3 = A’CD’ + A’B’C + B’C’D’+AB’C’+A’BC’D
C4 = A’CD’ + B’C’D’
C5 = A’BC’ + A’C’D’ + A’BD’ + AB’C’
C6 = A’CD’ + A’B’C + A’BC’ + AB’C’
 Conclusion

• There are two types of logic circuits

• Combinational
• Sequential
• Design Procedure
• Specification
• Formulation
• Optimization
• Technology Mapping
• Verification
• Examples
 Summary

• There are two types of logic circuits

• Combinational
• Sequential
• Design Procedure
• Specification
• Formulation
• Optimization
• Technology Mapping
• Verification
• Examples
Combinational Logic
Part II
 Objectives

• Arithmetic Circuits
• Adder
• Subtractor
• Carry Look Ahead Adder
• BCD Adder
• Multiplier
 Adder

• Design an Adder for 1-bit numbers?

 Adder

• Design an Adder for 1-bit numbers?

• 1. Specification:
2 inputs (X,Y)
2 outputs (C,S)
 Adder

• Design an Adder for 1-bit numbers?

• 1. Specification:
2 inputs (X,Y)
2 outputs (C,S)
• 2. Formulation:

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 Adder

• Design an Adder for 1-bit numbers?

• 1. Specification: 3. Optimization/Circuit
2 inputs (X,Y)
2 outputs (C,S)
• 2. Formulation:

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 Half Adder

• This adder is called a Half Adder

• Q: Why?

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 Full Adder

• A combinational circuit that adds 3 input bits to generate a

Sum bit and a Carry bit
• Two of the input variables, denoted as x and y
➔ represent the two significant bits to be added.
• The third input, z, represents the carry from the previous
lower significant position
 Full Adder

• A combinational circuit that adds 3 input bits to

generate a Sum bit and a Carry bit

X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 Full Adder

• A combinational circuit that adds 3 input bits to

generate a Sum bit and a Carry bit

Sum YZ
X Y Z C S
X 00 01 11 10
0 0 0 0 0 0 0 1 0 1 S = X’Y’Z + X’YZ’
0 0 1 0 1 + XY’Z’ +XYZ
1 1 0 1 0
0 1 0 0 1 =XYZ
0 1 1 1 0 Carry
YZ
1 0 0 0 1 X 00 01 11 10
1 0 1 1 0 0 0 0 1 0

1 1 0 1 0 1 0 1 1 1
1 1 1 1 1 C = XY + YZ + XZ
 Full Adder = 2 Half Adders

Manipulating the Equations:

S= XY Z
C = XY + XZ + YZ
 Full Adder = 2 Half Adders

Manipulating the Equations:

S=(XY)Z
C = XY + XZ + YZ
= XY + XYZ + XY’Z + X’YZ + XYZ
= XY( 1 + Z) + Z(XY’ + X’Y)
= XY + Z(X  Y )
 Full Adder = 2 Half Adders

Manipulating the Equations:

S=(XY)Z
C = XY + XZ + YZ = XY + Z(X  Y )

Think of
Z as a
carry in

Src: Mano’s Book

 Bigger Adders

• How to build an adder for n-bit numbers?

• Example: 4-Bit Adder
• Inputs ?
• Outputs ?
• What is the size of the truth table?
• How many functions to optimize?
 Bigger Adders

• How to build an adder for n-bit numbers?

• Example: 4-Bit Adder
• Inputs ? 9 inputs
• Outputs ? 5 outputs
• What is the size of the truth table? 512 rows! (29)
• How many functions to optimize? 5 functions (5 o/ps)
 Binary Parallel Adder

• A parallel adder is used add two numbers in parallel

form and to produce the sum bits as parallel outputs.
• To add n-bit numbers:
• Use n Full-Adders in parallel
• The carries propagates as in addition by hand
• Use Z in the circuit as a Cin

• 1 0 1 0 (Caryy Bits =C3C2C1C0)

• Carry out 0101 (1st number = A3A2A1A0)
= C4
• 1101 (2nd number = B3B2B1B0)
1 0010 (Sum bits = S3S2S1S0)
 Binary Parallel Adder

• To add n-bit numbers: (EX: n = 4)

• Use n Full-Adders in parallel (4 FAs required)
• The carries propagates as in addition by hand

Src: Mano’s Book

This adder is called ripple carry adder

• The parallel adder in which carry-out of each
full-adder is the carry-in to the next adder is
called a ripple carry adder.
• Observing the previous figure, we see that
• Output produce by firs full-adder(FA0) = S0 and C1
• S0 and C1 are not valid , until after the propagation delay of
FA0.
• Similarly, S1 is not valid, until after the cumulative
propagation delay of two full adders (FA0 and FA1) and so
on.
• Thus, total sum(parallel output) is not valid until after the
cumulative delay of all the adders.
• If two numbers are added such that no
carries occur between stages, then the
add time is simply the propagation time
through a single full-adder.
 Ripple Adder Delay

• Assume gate delay = T

• 8 T to compute the last
carry
• Total delay = 8 + 1 = 9T
• 1 delay form first half
adder
• Delay = (2n+1)T

Src: Course CD
 Subtraction (2’s Complement)

• How to build a subtractor using 2’s

complement?
 Subtraction (2’s Complement)

• How to build a subtractor using 2’s

complement?

Src: Mano’s Book

S = A + ( -B)
 Adder/Subtractor

• How to build a circuit that performs both

addition and subtraction?
 Adder/Subtractor

0 : Add
1: subtract

(SWITCH)

Src: Mano’s Book

Using full adders and XOR we can build an Adder/Subtractor!

 Binary Parallel Adder (Again)

• To add n-bit numbers:

• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

Src: Mano’s Book

This adder is called ripple carry adder

 Ripple Adder Delay

• Assume gate delay = T

• 8 T to compute the last
carry
• Total delay = 8 + 1 = 9T
• 1 delay form first half
adder
• Delay = (2n+1)T

How to improve?
 Carry Look Ahead Adder

• How to reduce propagation delay of ripple carry adders?

• The Look-ahead Carry Adder speeds up the process

• It examines all the input bits simultaneously and also generates the
carry-in bits for all the stages simultaneously.

• The method of speeding up the addition process is based on the

two additional function of Adder,
• Carry generate
• Carry propagate
 Carry Look Ahead Adder

• How to reduce propagation delay of ripple carry adders?

• Carry look ahead adder: All carries are computed as a function of
C0 (independent of n !)
• It works on the following standard principles:
• A carry bit is generated when both input bits Ai and Bi are 1, or
• When one of input bits is 1, and a carry in bit exists

Carry Cn Cn-1…….Ci……….C2C1C0
bits An-1…….Ai……….A2A1A0
Bn-1…….Bi……….B2B1B0
Carry Out
Sn Sn-1…….Si……….S2S1S0
 Carry Look Ahead Adder

Ai
Pi
Bi Si

Gi

Ci
Ci+1

Carry Generate Gi : Ci+1 = 1 when Gi = 1,

regardless of the input carry Ci
The internal signals are given by:
Pi = Ai Bi Carry Propagate Pi : Propagates Ci to Ci+1
Gi = Ai.Bi
Note: Pi and Gi depend only on Ai and Bi !
 Carry Look Ahead Adder

Ai
Pi
Bi Si
Ci

Gi
PiCi

Ci
Ci+1
Gi

The internal signals are given by: The output signals are given by:
Pi = Ai Bi Si = Pi Ci
Gi = Ai.Bi Ci+1 = Gi + PiCi
 Carry Look Ahead Adder

Ai
Pi
Bi Si

Gi
PiCi

Ci
Ci+1
Gi

• The carry outputs for various stages can be written as:

C1 = Go + PoCo
C2 = G1 + P1C1 = G1 + P1(Go + PoCo) = G1 + P1Go + P1PoCo
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
 Carry Look Ahead Adder

Conclusion: Each carry bit can be expressed in terms of

the input carry Co, and not based on its preceding carry
bit
Each carry bit can be expressed as a SOP, and can be
implemented using a two-level circuit, i.e. a gate delay
of 2T
Carry Look Ahead Adder

C0
A0
P0
B0 S0
Carry Look Ahead Block
G0

A1
B1 P1 S1
C1

G1
A2 C2
P2 S2
B2

G2
A3 C3
P3 S3
B3

G3 C4 C4
 Carry Look Ahead Adder

Steps of operation:
- All P and G signals are initially generated. Since both XOR
and AND can be executed in parallel. Total delay = 1T
- The Carry Look Ahead block will generate the four carry
signals C4, C3, C2, C1. Total delay = 2T
- The four XOR gates will generate the Sums. Total delay = 1T
Total delay before the output can be seen = 1T+2T+ 1T = 4T
Compared with the Ripple Adder delay of 9T, this is an
improvement of more than 100%
CLA adders are implemented as 4-bit modules, that can
together be used for implementing larger circuits
 BCD Adder

• BCD digits are valid for decimal numbers 0-9

• Addition of two BCD numbers will generate an output, that
may be greater than 1001 (9). (Invalid BCD as an output)

• In such cases, the BCD number 0110 is added to the

result as a correction step

• When adding two BCD numbers, the maximum result that

can be obtained is:
9 + 9 = 18 (10010)2
If we include a carry in bit, then the maximum result that can be
obtained is: 19 (10011)2

Both numbers 18 and 19 are invalid BCD digits. Therefore, a 6 needs

to be added to bring them to correct BCD format.
Adding two BCD numbers – Truth
Table

The truth table defines the outputs

when two BCD numbers are added
The function F is 1 for all invalid
BCD digits, and therefore acts as a
BCD verifier
To minimize the expression, a 5
variable can be used, or:
-A 4 variable k map can be used to
minimize the function F, and
-The result is ORed with CO, since
the function is always 1 whenever
CO is 1
Adding two BCD numbers –
Minimization

F
Z1Z0
Z3Z2 00 01 11 10
00 0 0 0 0
01 0 0 0 0
11 1 1 1 1
10 0 0 1 1

F = Z3Z2+ Z3Z1 + CO (Because F=1 when

C0 is 1)
Adding two BCD numbers – Circuit

B3 B2B1B0 A3A2A1A0

Cout 4-bit Binary Carry In

Adder
Z3 Z2 Z1 Z0
Z3Z2
F
F = Z3Z2 + Z3Z1 + CO

Z3Z1
0

Correction
Step 4-bit Binary
Adder

S3 S2 S1 S0
 Adding two BCD numbers - Steps

• The two 4-bit BCD inputs are added by the 4-bit binary
adder to produce the sum Z3Z2Z1Z0 (output)and a
Carry Out (Cout)
• For valid BCD number in output, the correction step
executes by adding 0000 to Z3Z2Z1Z0, and the output
remains the same
• For invalid BCD number in outputs, the correction step
adds 0110 to Z3Z2Z1Z0 to generate the corrected
output
• The output carry is the same as Cout
• If additional decimal digits need to be added, the BCD
adder can be cascaded, with the output carry of one
phase connected to the input of the other
 Binary Multiplication

• Similar to decimal multiplication

• Multiplying 2 bits will generate a 1 if both bits are equal to 1, and
will be 0 otherwise. Resembles an AND operation
Multiplying two 2-bit numbers is done as follows:

B1 B0
x A1 A0
----------------
This operation is an
A0B1 A0B0 addition, requires an
A1B1 A1B0 + ADDER
----------------------------------
C3 C2 C1 C0
 Binary Multiplication

• Therefore, for multiplying two 2-bit numbers, AND gates

and ADDERS will be sufficient

Half Adders