Verilog Codes

The logic of a module can be described in anyone (or a combination) of the following modeling styles:

→ Gate level Modeling

The module implemented in terms of logic gates and interconnections between these gates. This
is similar to drawing the actual circuit of the system but only on the code form. 1 Verilog supports
basic logic gates as predefined primitives. All logic circuits can be designed by using basic gates.

→Data flow Modeling

At this level the module is designed by specifying the data flow. The designer is aware of how
data flows between hardware registers and how the data is processed in the design.
→Behavioral Level Modeling
This is the highest level of abstraction provided by Verilog HDL. A module can be implemented
in terms of the desired design algorithm without concern for the hardware implementation details.
Designing at this level is very similar to C programming.

Summary:
• Gate-level modeling using instantiations of predefined and user-defined primitive gates. It is
very intuitive to a designer with a basic knowledge of digital logic circuit
• Dataflow modeling using continuous assignment statements with the keyword assign.
• Behavioral modeling using procedural assignment statements with the keyword always.

Recall the following

→ Parameter
A parameter is defining a constant which can be set when you use a module, which allows
customization of module during the instantiation process.
Example

Parameter add = 3’b010, sub = 2’b11;

Parameter n = 3;
Parameter [2:0] param2 = 3’b110;

→ Wires, Regs, and Parameters

Wires, regs and parameters are the data types used as operands in Verilog expressions.
Bit-Selection “x[2]” and Part-Selection “x[4:2]”
Bit-selects and part-selects are used to select one bit and a multiple bits, respectively,
from a wire, reg or parameter vector with the use of square brackets “[ ]”. Bit-selects and part-
selects are also used as operands in expressions in the same way that their main data objects are
used.
Example:

reg [7:0] x, y;
reg [3:0] z;
reg a;
a = x[7] & y[7]; // bit-selects
z = x[7:4] + y[3:0]; // part-selects
There are three (3) modelling style in Verilog. All examples’ programs use identifiers having multiple bit widths,
called vectors. The syntax specifying a vector includes within square brackets two numbers separated with a
colon.

The following Verilog statements specify two vectors:

output [0: 3] D;
➔ The statement declares an output vector D with four bits, 0 through 3.

wire [7: 0] SUM;

➔ The statement declares a wire vector SUM with eight bits numbered 7 through
0.7 → 0 (total of 8 bits)

MSB LSB
2^ 7 2^6 2^5 2^4 2^3 2^2 2^1 2^0
128 64 32 16 8 4 2 1

Example:

11111111 = 8 bits
255= 128 + 64 + 32 + 16 + 8 + 4 + 2 + 1

for Decimal Computation:

= 256 -1
= 255 → 11111111

The individual bits are specified within square brackets, so D [2] specifies bit 2 of D. It is also possible to address
parts (contiguous bits) of vectors.

Example:
module definition
module and4 (x, y, z);
input [3:0] x, y;

output [3:0] z;
assign z = x | y;
end module

Example code in vector:

Partial program for variable a:
module BehCode1 (W, X, Y, Z, a);
input W, X, Y, Z;

output a;
reg a;

always @ (W or X or Y or Z) // column a variable

begin
a = ((~(W) & ~(X) & ~(Z)) | (~(W)&Y) | (~(W) & X & Z) | (W & ~(X) &~(Y))) ;
// w'x’z’ + w’y + w’xz + wx’y’
end
endmodule

module TestBench;
reg W, X, Y, Z;

wire a;
initial
begin

$display ("W X Y Z a ");

W =1'b0; X =1'b0; Y =1'b0; Z =1'b0;
#15 $finish;
end
Practical Midterm Exam Question:

An ABCD-to-seven-segment decoder is a combinational circuit that add the binary by 10 then

converts a decimal digit in BCD. The seven outputs of the decoder (a, b, c, d, e, f, and g) select
the corresponding segments in the display, as shown on Figure 1. The numeric display chosen to
represent the decimal digit is shown in Table No.1. Using a truth table and Karnaugh maps, design
the BCD-to-seven-segment using a minimum number of gates.

Here is the following step to solve the given combinational logic design:

1. Specification, you must know the following specification in a circuit. Assume the inputs are W, X,
Y and Z.
where:
• Variable W is the most significant bit (MSB)
• Variable Z is the least significant bit (LSB)

WXYZ = 4 variables

2 ^ 4 = 16 rows / lines

As shown in figure 1, the output segment labelled a, b, c, d, e, f and g.

Figure 1: Seven (7) Segment Display

2. Formulation – you need to convert the specifications into a variety of forms. The form is to
construct a Truth table. The table below shows the conversion of binary number to decimal number.

Table 1: Truth Table for BCD

Sample Boolean Expression
1st seven segment → a1 =d1=e1=f1=f1 GND b1= c1= VCC
2nd seve segment → a1= mo + m2 +m3+m5 + m7
a1= x’y’z’ + x’yz’ + x’yz +‘ xy’z + xyz

➔ K=mapping

m0 m1 m2 m3

m4 m5 m7 m6

m 12 m 13 m 15 m14

m8 m9 m 11 m10

➔ Simplified Boolean expression in SOP form

Below are the sample cathode 7-segment display

 Figure 2 shows the circuit design using basic gates for 7 segment using LEDs.

Figure 2: Sample basic logic circuit

Figure 3 shows the combinational Gates. The circuit shows the display in binary coded
decimal using 7-segment display as shown on figure 1.

Add
files

Figure 3: Block diagram of the Combinational Gates

Requirements:
• Circuit Diagram as shown on figure 2 and figure 3.
• Verilog program either dataflow or behavioral Modeling
styles
• Documentation with figure and description
Circuit Diagram
K Mapping + Boolean

Output a: X’ Z’ + X’ Y + XZ

YZ

00 01 11 10

0 1 0 1 1
X
1 0 1 1 0
Output b: X’ + Y’ Z’ + YZ

YZ

00 01 11 10

0 1 1 1 1
X
1 1 0 1 0

Output c: Y’ + Z + X

YZ

00 01 11 10

0 1 1 1 0
X
1 1 1 1 1

Output d: X’ Z’ + X’ Y + Y Z’ + X Y’ Z

YZ

00 01 11 10

0 1 0 1 1
X
1 0 1 0 1
Output e: X’ Z’ + Y Z’

YZ

00 01 11 10

0 1 0 0 1
X
1 0 0 0 1

Output f: Y’ Z’ + X Y’ + X Z’

YZ

00 01 11 10

0 1 0 0 0
X
1 1 1 0 1

Output g: X’ Y + X Y’ + X Z’

YZ

00 01 11 10

0 0 0 1 1
X
1 1 1 0 1
Verilog Program W/ Output