DIGITAL CIRCUIT DESIGN

18B11EC215
Lecture-12
Binary Adders and Subtractors

1
 Outlines
▪ Introduction
▪ Analysis Procedure
▪ Design Methods
▪ Half Adder
▪ Full Adder
▪ Half Subtractor
▪ Full Subtractor
▪ References

2
 Introduction [1-3]
▪ Digital circuits are divided into two broad categories:
1. Combinational Logic Circuits
2. Sequential Logic Circuits
▪ Combinational Logic Circuit: In these circuits, the outputs at
any instant of time depend upon the inputs present at that instant
of time. This means there is no memory in these circuits.

inputs :: Combinational :: outputs

Logic
 Introduction [1-3]
▪ Sequential Logic Circuit: In these circuits, the outputs at any
instant of time depend upon the present inputs as well as past
inputs/outputs. This means that there are elements used to store
past information. These elements are known as memory.

inputs :: Combinational :: outputs

Logic
Memory

▪ A sequential logic system may have combinational logic

sub-systems.
 Analysis Procedure [1]
▪ A combinational circuit is given, analyze its function?

A A+B
B F1 = (A+B).(A'+B')

F2 = (A'+B')' = A.B
A'+B'
Steps:
1. Label the inputs and outputs.
2. Obtain the functions of intermediate
points and the outputs.
3. Draw the truth table.
4. Deduce the functionality of the circuit half adder.
 Design Methods [1]
▪ Different combinational circuit design methods:
❖ Gate-level method (with logic gates)
❖ Block-level design method

▪ Design methods make use of logic gates and useful functional

blocks.
❖ These are available as Integrated Circuit (IC) chips.
 Design Methods [1]
▪ Type of IC chips (based on packing density):
❖ Small-scale integration (SSI): up to 12 gates
❖ Medium-scale integration (MSI): 12-99 gates
❖ Large-scale integration (LSI): 100-9999 gates
❖ Very large-scale integration (VLSI): 10,000-99,999 gates
❖ Ultra large-scale integration (ULSI): > 100,000 gates

▪ Main objectives of circuit design:

(i) Reduce cost
Reduce number of gates (for SSI circuits)
Reduce IC packages (for complex circuits)
(ii) Increase speed
(iii) Design simplicity (reuse blocks where possible)
 Half Adder [2]
▪ A logic circuit for the addition of two one-bit numbers is
referred to as an half-adder.
▪ Design procedure:
1) State Problem
Example: Build a Half Adder to add two bits
2) Determine and label the inputs & outputs of circuit.
▪ Example: Two inputs and two outputs labelled, as follows:

X Half S
Y Adder C
(X + Y)

3) Draw truth table.

Gate-level Design: Half Adder [2]
4) Obtain simplified Boolean function.
Example: C = X.Y
S = X'.Y + X.Y' = X⊕Y

5) Draw logic diagram.

X
S
Y

Half Adder
 Full Adder [2]
▪ Half-adder adds only two bits and there is no provision to add a
carry coming from the lower order bits when multibit addition is
performed.
▪ To add two binary numbers, we need to add 3 bits (including the
carry).
▪ Example:

▪ Need Full Adder (as it can be made from two half-adders).

X
Full S
Y
Z Adder C
(X + Y + Z)
 Full Adder [2]
▪ Truth table:
Note:
Z - carry in (to the current position)
C - carry out (to the next position)

C
YZ
X
00 01 11 10
0 1

1 1 1 1

YZ
S
Using K-map, simplified SOP form: X
00 01 11 10
0
• C = X.Y + X.Z + Y.Z 1 1

1 1 1
• S = X'.Y'.Z + X'.Y.Z'+X.Y'.Z'+X.Y.Z
 Full Adder [3]
▪ Alternative formulas using algebraic manipulation:
C = X.Y + X.Z + Y.Z
= X.Y + X (Y+Y').Z + (X+X')YZ
= X.Y + X YZ+XY'Z + X YZ +X'YZ
= X.Y (1+Z) + (X⊕Y).Z
= X.Y + (X⊕Y).Z
S = X'.Y'.Z + X'.Y.Z' + X.Y'.Z' + X.Y.Z
= X'.(Y'.Z + Y.Z') + X.(Y'.Z' + Y.Z)
= X'.(Y⊕Z) + X.(Y⊕Z)'
= X⊕(Y⊕Z) or (X⊕Y)⊕Z
 Gate-level Design: Full Adder [3]
▪ Circuit for following formulas:
C = X.Y + (X⊕Y).Z
S = (X⊕Y)⊕Z
X (X⊕Y)
Y S

(XY)

▪ Full Adder is made from two Half-Adders (+ OR gate).

 Full Adder [3]
▪ Circuit for following formulas:
C = X.Y + (X⊕Y).Z Block diagrams.

S = (X⊕Y)⊕Z
X (X⊕Y)
X Sum X
Y Y Sum S
Y
Half Half
Adder Adder
(X.Y)
Carry Carry
C

Full Adder made from two Half-Adders (+ OR gate).

 Half Subtractor [2]
1) Obtain simplified Boolean function.
B (Borrow) = X'.Y
D (Difference) = X'.Y + X.Y' = X⊕Y
2) Draw logic diagram.

X
D
Y

B
 Full Subtractor [2]
▪ A full subtractor is a
BOUT D
combinational circuit that X Y Bin
(Borrow) (Difference)
performs subtraction involving
three bits, namely minuend, 0 0 0 0 0
subtrahend, and borrow-in (Bin). 0 0 1 1 1
The logic symbol and truth table 0 1 0 1 1
are shown here. 0 1 1 1 0
Symbol: 1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
 Full Subtractor [2]
• Draw K-maps using the previous truth table and determine
the simplified Boolean expressions-
 Full Subtractor [2]
▪ Draw the logic diagram.
▪ The implementation of full adder using 1 XOR gate, 3 AND
gates, 1 NOT gate and 1 OR gate is as shown below.
 Full Subtractor [3]
▪ Alternative formulas using algebraic manipulation:
Bout = X'.Y + X'. BIN + Y. BIN
= X'.Y + (X' + Y). BIN
= X'.Y + ((X⊕Y)' + X'.Y). BIN
= X'.Y + (X⊕Y)'. BIN + X'.Y. BIN
= X'.Y + (X⊕Y)'. BIN

D= X'.Y'.BIN + X'.Y.BIN ' + X.Y'.BIN ' + X.Y.BIN

= X' .(Y'.BIN + Y.BIN ') + X.(Y'.BIN ' + Y.BIN)
= X'.(Y⊕BIN) + X.(Y⊕BIN)'
= X⊕(Y⊕BIN) or (X⊕Y)⊕BIN
 Full Subtractor [3]
▪ Circuit for following formulas:
BOUT = X'.Y + (X⊕Y)'.BIN
Diff = (X⊕Y)⊕BIN

Full Subtractor made from two Half-Subtractors (+ OR gate).

 Full Subtractor [3]
▪ Circuit for following formulas:
BOUT = X'.Y + (X⊕Y)'.BIN
Diff = (X⊕Y)⊕BIN Block diagrams.

Full Subtractor made from two Half-Subtractors (+ OR gate).

 References
[1] M. Morris Mano and Michael D. Ciletti, “Digital Design with
an Introduction to the Verilog HDL”, 5th Edition, Pearson
Education, 2013.

[2] R. P. Jain, “Modern Digital Electronics”, 4th Edition, Tata

McGraw-Hill Education, 2009.

[3] A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI,

Fourth Edition.

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