Chapter4: Combinational Logic

Lecture2- Design BCD to Excess-3 Code Converter using Classical

Design Procedure
Engr. Arshad Nazir, Asst Prof
Dept of Electrical Engineering
Fall 2023 SEECS 1
 Objectives
• Study design steps for Combinational Circuits
• Design Combinational Logic Circuits of Moderate Complexity i.e
BCD to Excess-3 Code Converter using Classical Design Method

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 Design Procedure
• The design procedure of combinational circuits involves following
steps
➢State the problem (Circuit specifications)
➢From the circuit specifications determine the inputs and outputs
for the circuit design
➢The input and output variables are assigned alphabetic symbols
➢Derive the truth table that gives the relationship between inputs
and outputs
➢Derive the simplified Boolean functions (simplify by algebraic
manipulation or K-map method) for each output variable as a
function of input variables
➢Draw the logic diagram and verify the correctness of the design
• The design should be optimized i.e use minimum gates with fewer fan
in of gates and lesser propagation delay. This will result in low cost but
fast design.

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 Code Conversion example
• Different digital systems use different types of codes
• It is sometimes necessary to use the output of one system as the
input to another
• A conversion circuit must be inserted between the two systems if
each uses different codes for the same information
• A code converter is a circuit that makes the two systems compatible
even though each uses a different binary code
• To convert from binary code A to binary code B, the input lines (of
combinational circuit) must supply the bit combination of elements as
specified by code A and the output lines must generate the
corresponding bit combination of code B

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 Code Conversion Example: BCD to
Excess-3 Code Converter
• Each code uses four bits to represent a decimal digit, there must be
four input variables and four output variables
• Designate the four input binary variables by the symbols A,B,C,D and
the four output variables by w, x, y and z.
• The truth table relating the input and output variable is made (shown
in next slide)
• Four binary variables have 16 possible bit combinations but only 10
are listed in the truth table as remaining 6 combinations not listed are
don’t care conditions. These have no me.aning in BCD

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Code conversion Example :Truth
Table
Input Output
BCD Excess-3 Code
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

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 Map Simplification of Output
Functions
• There are four outputs, each as a function of four input variables.
• There are four maps, each representing one of the outputs, to obtain
simplified Boolean functions.
• The 1’s marked inside the squares are obtained from the minterms that
make the output equal to 1
• The 1’s are obtained from the truth table by going over the output
columns one at a time.
• The 6 don’t care minterms 10 through 15 are marked with an X or d.

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BCD to Excess-3 Code Converter
• The simplified functions
➢z = D'
➢y = CD +C'D‘
➢x = B'C + B'D+BC'D'
➢w = A+BC+BD
• A two-level logic diagram may be obtained directly from the above
Boolean expressions but there are various other possibilities for logic
diagram that implements this circuit
• Another implementation
➢z = D'
➢y = CD +C'D' = CD + (C+D)'
➢x = B'C + B'D+BC'D' = B'(C+D) +B(C+D)'
➢w = A+BC+BD

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 BCD to Excess-3 Code Converter
• The purpose this manipulation is to use common gates for two or
more outputs
• This is implemented with three levels of gates
• OR gate with output C+D is used to implement partially each of three
outputs
• Implementation with original sum of products require seven AND
gates and three OR gates whereas after manipulation we require four
AND gates and four OR gates
• In this way the logical circuit has been implemented in a much
economical way.

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 Half Adder
• Half adder adds two binary bits and produces SUM and Carry so it
requires two inputs and two outputs
• 0+0=0 ; 0+1=1 ; 1+0=1 ; 1+1=10
• The input variables designate the augend and addend bit, the output
variables produce the sum (S) and carry (C)
• The truth table for half adder is shown. The C output is 1 only when
both inputs are 1. The S output represents the least significant bit of
the sum

x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

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 Half Adder Output Expressions
• The simplified sum of products expressions are:
➢S = x'y+xy'
➢C = xy
• It can be implemented in sum of products. It can also be implemented
with an exclusive-OR and an AND gate
➢S=xy= (x+y)(x'+y')
➢S' = xy+x'y'= C+ x'y'
➢S = (C+x'y')'
➢C = xy= (x'+y')'

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Fall 2023 15
 Full Adder
• A Full-Adder (FA) is a combinational circuit that forms the arithmetic
sum of three bits (three input bits).
➢Two of the input variables x, y represents the two significant bits
to be added
➢The third input z represents the carry bit from the previous lower
significant position
➢Two output bits are necessary designated by the symbol S for sum
and C for carry
• When all input bits are 0, the output is 0 x y z c s
0 0 0 0 0
• The S output is equal to 1 when only one 0 0 1 0 1
input is equal to 1 or when all three inputs 0 1 0 0 1
are equal to 1 0 1 1 1 0
1 0 0 0 1
• The C output has a carry of 1 if two or 1 0 1 1 0
three inputs are equal to 1 1 1 0 1 0
1 1 1 1 1

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 C

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Simplified Output Expressions for Full
Adder
• The simplified expressions for full adder are
• S = x' y' z + x' y z' + x y' z' + x y z
• C = xy + xz + yz

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 Full Adder with Two Half Adders
• Full adder can also be implemented with two half adders and an OR gate. The S
output from the second half adder is the exclusive-OR of z and the output of
the first half adder giving
• S = z  (x  y)
= z'(xy'+x'y)+z(xy'+x'y)'
=z'(xy'+x'y)+z(xy+x'y')
= xy'z'+x'yz'+xyz+x'y'z
• C = z(xy'+x'y)+xy
= xy'z+x'yz+ xy

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The End

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