 Computations of Memory chips Computation of Memory chips for Scalable Memories

Number of Words =N
Width of Word =W
Available Chip size =NxW
Required memory size = NI x WI

NI
p= Where NI ≥ N
N

q= W
I
Where WI ≥ W
W

p *q, N x W Chips are needed for NI x WI memory size

denotes the smallest integer grater than or equal

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 1

 Computations of Memory chips There are different types of organization of N1 x W1 –
 Different memory Organizations memory using N x W –bit chips

Case 1: If NI > N & WI = W

NI
Increase number of words by the factor of p = N

Case 2: If NI = N & WI > W

q
Increase the word size of a Memory by a factor of = W I

Case 3: If NI > N & WI > W

Increase number of words by the factor of p &
Increase the word size of a Memory by a factor of q

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 2

1. A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer system

needs 2K bytes of RAM, 4K bytes of ROM, and four interface units, each with four registers. A

memory-mapped I/O configuration is used. The two highest-order bits of the address bus are

assigned 00 for RAM and 10 for interface registers. a. How many RAM and ROM chips are

needed? b. Draw a memory-address map for the system. c. Give the address range in hexadecimal

for RAM, ROM and interface.

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 3

 Computations of Memory chips Example1
 Different memory Organizations
 Example-1 How many 1024x 8 RAM chips are needed
to provide a memory capacity of 2048 x 8?
Available Chip size = N x W = 1024 x 8
Required memory size = NI x WI = 2048 x 8
NI 2048
p= = = 2 Where NI ≥ N
N 1024

q= WI = 8 Where WI ≥ W
W = 1
8

p * q, N x W Chips are needed for NI x WI memory size

2 *1 =2, 1024 x 8 RAM Chips are needed for 2048x 8 memory size

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 4

How many 1024x 8 RAM chips are needed to
provide a memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x+ y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W
1 RAM 1024 x 8 2048 x 8 2 1 2 10 1 0 11
How many 1024x 8 RAM chips are needed to
provide a memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x+ y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W
1 RAM 1024 x 8 2048 x 8 2 1 2 10 1 0 11
How many 1024x 8 RAM chips are needed to
provide a memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x+ y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W
1 RAM 1024 x 8 2048 x 8 2 1 2 10 1 0 11

Hexadecimal address Address bus

Component
From To 15 14 13 12
11 10 9 8 7 6 5 4 3 2 1 0
RAM[1,1] 0000 3FF 0 x x x x x x x x x x
RAM[2,1] 400 7FF 1 x x x x x x x x x x
How many 1024x 8 RAM chips are needed to
provide a memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x+ y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W
1 RAM 1024 x 8 2048 x 8 2 1 2 10 1 0 11

Hexadecimal address Address bus

Component
From To 15 14 13 12
11 10 9 8 7 6 5 4 3 2 1 0
RAM[1,1] 0000 3FF 0 x x x x x x x x x x
RAM[2,1] 0400 7FF 1 x x x x x x x x x x
2. The clock of the processor runs at 200 MHz. The following table gives instruction
frequencies for Benchmark B, as well as how many cycles the instructions take, for the
different classes of instructions. For this problem, we assume that (unlike many of today's
computers) the processor only executes one instruction at a time.
Instruction Type Frequency Cycles
Loads & Stores 20% 3 cycles
arithmetic's 30% 5cycles
Square root 50% 6cycles

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 9

If we say that there are 100 instructions, then:20 of them will be loads and stores.
30 of them will be arithmetic instructions.50 of them will be all others.

(20 * 3) + (30 * 5) + (50 * 6) = 510 cycles/100 instructions

Therefore, there are 5.1 Cycles per instruction.

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 10

3. Cache management policies problem refer the below
link
1. https://youtu.be/_Hh-NcdbHCY
2. https://youtu.be/7lxAfszjy68

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 11

 Study the following topics
1. Memory interleaving pros and cons , significance
2. Hardwired and micro programmed control unit
3. merits and de-merits of 1-bus micro architecture vs 2 bus
micro architecture.
4. Characteristics of memory.
5. process of an instruction diagram and states

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 12