Computer Architecture and

Organization

• Course Code: BCSE205L

• Course Type: Theory (ETH)
• Slot: D2+TD2
• Timings:

Monday 16:00-16:50
Wednesday 17:00-17:50
Thursday 14:00-14:50
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
 Syllabus- Module 4
Module:4 Memory System Organization and Architecture 7 hours

Memory systems hierarchy: Characteristics, Byte Storage methods,

Conceptual view of memory cell - Design of scalable memory using
RAM’s- ROM’s chips - Construction of larger size memories - Memory
Interleaving - Memory interface address map- Cache memory: principles,
Cache memory management techniques, Types of caches, caches misses,
Mean memory access time evaluation of cache.

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore

 Module:4
Memory System Organization and Architecture
Memory_Address_Map

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Memory Block Diagram

• Capacity of the Memory is 128 words

of eight bits
• 7 bit Address (Because number of
words=128, 2^7=128)
• 8 –bit bidirectional data bus
(Because, number of bits or cell in
each word is 8)

• The 8-bit bidirectional data bus allows the transfer of data

• either from memory to CPU during a read operation
• or from CPU to memory during a write operation
•The read and write inputs specify the memory operation, and the two chip select (CS)
control inputs are for enabling the chip only when the microprocessor selects it.
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Memory Block Diagram
• The primary component of the main memory is RAM
integrated circuit chips, but a portion of memory may be
constructed with ROM chips.
• A ROM memory is used for keeping programs and data that
are permanently resident in the computer.
• Apart from the permanent storage of data, the ROM portion
of main memory is needed for storing an initial program
called a bootstrap loader.
ROM chips are also available in a variety of sizes and are also used as per the system requirement.
The block diagram demonstrates the chip interconnection in a 512 * 8 ROM chip.

The primary function of the bootstrap loader program is to start the computer software operating when power is
turned on.
• A ROM chip has a similar organization as a RAM chip. However, a ROM can only perform read operation; the
data bus can only operate in an output mode.
• The 9-bit address lines in the ROM chip specify any one of the 512 bytes stored in it.
• The value for chip select 1 and chip select 2 must be 1 and 0 for the unit to operate. Otherwise, the data bus is
said to be in a high-impedance state. Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Organization of 16 x 8 memory
In given diagram
• there are 16 memory locations named as
w0, w1, w3…w15.
• Each location can store at most 8 bits of
data (b0, b1, b3… b7).

• Each row of the cell is a memory word.

• The memory words are connected to a common
line termed as word line.
• The word line is activated based on the address
it receives from the address bus.
• An address decoder is used to activate a word
line.

• The cells in the memory are connected by two bit lines (column wise).
• These are connected to data input and data output lines through sense/ write circuitry.

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore

Organization of 16 x 8 memory

• Read Operation: During read

operation the sense/ write circuit reads
the information by selecting the cell
through word line and bit lines. The
data from this cell is transferred
through the output data line.

• Write Operation: During write operation,

the sense/ write circuitry gets the data and
writes into the selected cell.

• The data input and output line of sense / write circuit is connected to a bidirectional data line.
It is essential to have n address bus lines to read 2^n words
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
 128 x 8 memory chips 1024 x 1 memory chips
• It has got 128 memory words of size • If it is organized as a 1024 x 1 memory
8 bits. chips,
• So the size of data bus is 8 bits and • then it has got 1024 memory words of size
the size of address bus is 7 bits 1 bit only.
(2^7=128). • Therefore, the size of data bus is 1 bit and
• The storage organization of 128 x 8 the size of address bus is 10 bits
memory chip is shown in the below (2^10=1024).
figure.

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore

Memory Address Map
 Address lines: to identify number of memory locations in the chip
according to the following relation: n-address line Ex: if n=9 then the chip
contains 2^9 = 512 locations.

 Data lines: represent data input / output lines in a memory chip. Ex: 2M x 8
of memory has 8-data lines and 21 address lines since, 2M= 2 x 2^20 = 221

 Control lines: memory chips are provided two control lines,

 R/W ̅ : R/ ̅W line is used to specify the required operation about read or
write.
 CS ̅. The CS ̅ (Chip Select) line is required to select a given chip in a
multi- chip memory system.
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Memory Address Map
• The maximum size of main memory that can be used in any computer is determined by
the addressing scheme.
• A computer that generates 16-bit address is capable of addressing upto 2^16 which is
equal to 64K (65,536) memory location.
• Similarly, for 32 bit addresses, the total capacity will be 2^32 which is equal to 4G
memory location.
• In some computer, the smallest addressable unit of information is a memory word and the
machine is called word-addressable.
• In some computer, individual address is assigned for each byte of information, and it is
called byte-addressable computer.
• In this computer, one memory word contains one or more memory bytes which can be
addressed individually. A byte addressable 32-bit computer, each memory word
contains 4 bytes. Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Memory Address Map

Important Note:

Main memory Expansion:

• Main memory can be expanded either in word size (horizontal) or by
increasing number of words (vertical).
• Horizontal Expansion (increase number of data)
• Vertical Expansion (increase number of address line)
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Main memory Expansion:
• Main memory can be expanded either in word size (horizontal) or by increasing number of words (vertical).
• Horizontal Expansion (increase number of data)
• Vertical Expansion (increase number of address line)
Implement (Design) a 2k bytes memory using 2k x 4 bit chip RAM in a CPU has 8 bit data lines?

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore

Main memory Expansion:
• Main memory can be expanded either in word size (horizontal) or by increasing number of words (vertical).
• Horizontal Expansion (increase number of data)
• Vertical Expansion (increase number of address line)

Ex: Implement a memory with 4KB x8 using 2KB

x8 RAM chips, if ?

Final Memory is 4KB x8 so, the CPU has 14 address lines

(Since 4KB=2^2x2^10=2^12
Here it formed with two 2KB x8 chips, to represent each individual we required another one.
And, for representation data bits of individual chip (two more address lines)

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore

How many 1024x 8 RAM chips are needed to provide a
memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

1 RAM 1024 x 8 2048 x 8 2 1 2 10 1 0 11

• x->number of address lines

• y(p=2^y)-> to select one among the same type of memory
• z->To select the type of the memory
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
How many 1024x 8 RAM chips are needed to provide a
memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

1 RAM 1024 x 8 2048 x 8 2 1 2 10 1 0 11

• x->number of address lines

• y(p=2^y)-> to select one among the same type of memory
• z->To select the type of the memory
How many 1024x 8 RAM chips are needed to provide a
memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

1 RAM 1024 x 8 2048 x 8 2 1 2 10 1 0 11

Hexadecimal address Address bus

Component
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM[1,1] 0000 3FF 0 x x x x x x x x x x
RAM[2,1] 400 7FF 1 x x x x x x x x x x

• x->number of address lines

• y(p=2^y)-> to select one among the same type of memory
• z->To select the type of the memory
How many 1024x 8 RAM chips are needed to provide a
memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

1 RAM 1024 x 8 2048 x 8 2 1 2 10 1 0 11

Hexadecimal address Address bus

Component
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM[1,1] 0000 3FF 0 x x x x x x x x x x
RAM[2,1] 0400 7FF 1 x x x x x x x x x x

• x->number of address lines

• y(p=2^y)-> to select one among the same type of memory
• z->To select the type of the memory
How many 1024x 8 RAM chips are needed to provide a
memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

1 RAM 1024 x 8 2048 x 8 2 1 2 10 1 0 11

Hexadecimal address Address bus

Component
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM[1,1] 0000 3FF 0 x x x x x x x x x x
RAM[2,1] 0400 7FF 1 x x x x x x x x x x

• x->number of address lines

• y(p=2^y)-> to select one among the same type of memory
• z->To select the type of the memory
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Implement (Design) a 128x16 bit RAM using 128 x 4 bit
chip RAM?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

1 RAM 128x 4 128 x 16 1 4 4 7 0 0 7

• x->number of address lines

• y(p=2^y)-> to select one among the same type of memory
• z->To select the type of the memory
Implement (Design) a 128x16 bit RAM using 128 x 4 bit
chip RAM?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

1 RAM 128x 4 128 x 16 1 4 4 7 0 0 7

• x->number of address lines

• y(p=2^y)-> to select one among the same type of memory
• z->To select the type of the memory
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore
Design of 512×8 RAM using 128×8 RAM
Basic RAM size = 128 x 8
Required RAM size = 512 x 8
Desired RAM Size𝑥𝑥
Number of chips required =
Basic RAM Size

512x8
= = 4 chips
128x8

Available Address Bits from given RAM chip: 512 x 8 =2^7x 8

So, available address bits from given RAM: 7bits
Required Address Bits:
Required Size is 512 x 8 => 512 x 8= 2^9 x 8
Therefore, 9 bit address is required

Note: Decoder Size: If the number of words is increasing there will be a need for a decoder. In this case
number of words is increasing (from 128 to 512).
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore Source: Internet
How do I design a 8Kx8 bit
memory system by using 2Kx8
bit memory chips? The address
bus width is 16 bits

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore Source: Internet

How do I design a 4Kx8 bit
memory system by using 1Kx4
bit memory chips? The address
bus width is 16 bits

Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore Source: Internet

How many 1024x 4 RAM chips are needed to provide a
memory capacity of 1024 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

1 RAM 1024 x 4 1024 x 8 1 2 2 10 0 0 10

Hexadecimal address Address bus

Component
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM[1,1] RAM[1,2] 0000 3FF x x x x x x x x x x
How many 1024x 4 RAM chips are needed to provide a
memory capacity of 2048 x 8?
No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

1 RAM 1024 x 4 2048 x 8 2 2 4 10 1 0 11

Hexadecimal address Address bus

Components organization
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM[1,1] RAM[1,2] 000 3FF 0 x x x x x x x x x X
RAM[2,1] RAM[2,2] 400 7FF 1 x x x x x x x x x X
Example (Containing different types of rams
A computer employs RAM chips of 1024 x 8 and ROM chips of 2048 x 4. The computer
system needs 2K bytes of RAM, and 2K bytes of ROM . The highest-order bit of the address
bus is assigned 0 for RAM and 1 for ROM.
a). How many RAM and ROM chips are needed?
b). How many lines of the address bus must be used to access 2048 bytes of RAM and 2048
bytes of ROM? How many of these lines will be common to all chips?
c). How many lines must be decoded for chip select? Specify the size of the decoder
d). Draw a memory-address map for the system.
e). Draw a memory-address map for the system and Give the address range in hexadecimal
for RAM, ROM
Example (Containing different types of rams
A computer employs RAM chips of 1024 x 8 and ROM chips of 2048 x 4. The
computer system needs 2K bytes of RAM, and 2K bytes of ROM . The highest-
order bit of the address bus is assigned 0 for RAM and 1 for ROM.
a). How many RAM and ROM chips are needed?
b). How many lines of the address bus must be used to access 2048 bytes of RAM
and 2048 bytes of ROM? How many of these lines will be common to all chips?
c). How many lines must be decoded for chip select? Specify the size of the
decoder
d). Draw a memory-address map for the system.
e). Draw a memory-address map for the system and Give the address range in
hexadecimal for RAM, ROM
Example: A computer employs RAM chips of 1024 x 8 and ROM chips of 2048 x
4. The computer system needs 2K bytes of RAM, and 2K bytes of ROM . The
highest-order bit of the address bus is assigned 0 for RAM and 1 for ROM.

RAM ROM
Available Chip size = N x W = 1024 x 8 = 2048x 4
Required memory size = NI x WI = 2048 x 8 = 2048 x 8

2048 NI 2048
NI = 1
p= = = 2 p= =
1024 N 2048
N
WI q= WI = 8
q= = 8
= 1 W = 2
W 4
8

p * q, N x W Chips are needed for NI x WI memory size

2 *1 =2, 1024 x 8 RAM Chips are needed for 2048x 8 memory size
1 *2 =2, 2048 x 4 ROM Chips are needed for 2048x 8 memory size
How many 1024x 4 RAM chips are needed to provide A computer employs RAM
chips of 1024 x 8 and ROM chips of 2048 x 4. The computer system needs 2K
bytes of RAM, and 2K bytes of ROM . The highest-order bit of the address bus is
assigned 0 for RAM and 1 for ROM.

No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

2 RAM 1024 x 8 2048 x 8 2 1 2 10 1 1 11

2 ROM 2048 x 4 2048 x 8 1 2 2 11 0 1 12
How many 1024x 4 RAM chips are needed to provide A computer employs RAM chips of 1024 x 8 and
ROM chips of 2048 x 4. The computer system needs 2K bytes of RAM, and 2K bytes of ROM . The
highest-order bit of the address bus is assigned 0 for RAM and 1 for ROM.

No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

2 RAM 1024 x 8 2048 x 8 2 1 2 10 1 1 12

2 ROM 2048 x 4 2048 x 8 1 2 2 11 0 1 12

Hexadecimal address Address bus

Components organization
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM[1,1] 000 3FF 0 0 x x x x x x x x x x
RAM[2,1] 400 7FF 0 1 x x x x x x x x x x
ROM[1,1] ROM[1,2] 1 x x x x x x x x x x x
 How many 1024x 4 RAM chips are needed to provide A computer employs
RAM chips of 1024 x 8 and ROM chips of 2048 x 4. The computer system
needs 2K bytes of RAM, and 2K bytes of ROM . The highest-order bit of the
address bus is assigned 0 for RAM and 1 for ROM.

No. of Required p= q= x y z
Memory Memory Available memory N = 2 p = 2 T= 2z x + y+ z
x y

NI WI p *q
Types= Type Chip size size =
T =NxW NI x WI N W

2 RAM 1024 x 8 2048 x 8 2 1 2 10 1 1 12

2 ROM 2048 x 4 2048 x 8 1 2 2 11 0 1 12

Hexadecimal address Address bus

Components organization
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM[1,1] 000 3FF 0 0 x x x x x x x x x x
RAM[2,1] 400 7FF 0 1 x x x x x x x x x x
ROM[1,1] ROM[1,2] 1 x x x x x x x x x x x
Dr. Venkata Phanikrishna B, SCOPE, VIT-Vellore