Memory Organisation

Memory is required in a computer system to store information (instructions or data) during input
or output operation.
Memory is an arrangement of cells in rows and columns

There are m rows and n columns where rows denote words and columns denote the bits per
word.
For example if a memory whose capacity is 1k it means that there are 1024 words where each
word is storing 8 bit of information.

1024 by 8 bit memory device

The no. of address lines is related to the total capacity through the relation 1024= 2n and
therefore n=10
For example 2k x 4 means that there are 2048 words.
In general, any memory device is shown with the following diagram-
M address lines and n data lines and some control lines.

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 1 0 0
Internal Architecture for typical memory

first block is the memory with m words and n locations and input buffer, output buffer, address
decoder and an arrangement of and gates.
Here when CS=1 and WR=1 then RD=0 this will cause the i/p gate 1 as 1,1,1 and its o/p will be 1
and this output is connected to the enable pin of the input buffer so the input data will be
stored in the specified location.

Similarly, when CS=1, RD=1 and WR=0, gate 2 gets activated enabling output buffer thus
reading and writing operation is performed.
Memory hierarchy
Memory hierarchy is the arrangement of memory based on cost, capacity and speed. The total
memory capacity of a computer is the hierarchy of memory devices. The goal of every memory
system is to add write memory while keeping an acceptable level of performance and be cost
effective. We can achieve these goals by having different memory types from ranging from slow
but high capacity secondary memory to fast but to a relatively faster main memory to even
smaller and faster cache memory.

Two level memory hierarchy-

In two level memory hierarchy, main memory and secondary memory is used, where main
memory communicates with the CPU directly. Secondary memory Cannot communicate with
the CPU directly. With the help of an input processor, it can communicate with the main
memory which in turn communicates with the CPU. Programmes which are not currently
needed are transferred back to secondary memory to create more space for current
programmes. Main memory is high speed, high cost but less space while secondary memory is
low speed, less cost but more space.

3 Level Memory Hierarchy

In three level memory hierarchy, cache memory is also added with main and secondary
memory such that CPU can communicate directly with cache, while cache can
communicate with main memory which in turn communicates with secondary memory.
The cache memory is split i.e separate cache memory is used to store instructions and
data.

4 level Memory Hierarchy

Read and Write Process

Read process-
1. Chip is selected.
2. Memory address is provided
3. Road command is issued by the control unit
4. The data is made available on the data bus.

Write process-
1. Chip is selected
2. Memory address is provided
3. Data is sent on the data bus as an input
4. Write command is issued.
Horizontal and vertical memory expansion
If the requirement for memory is larger that the available capacity then one can cascade
multiple memory chips in order to get the desired capacity. This concept is called
memory expansion.
Numerically,
No. of memory chips required = required capacity/given capacity

Say we want to have a memory of 1K X 32 and we have 1K X 8 memory chips available.

Therefore, req. no. of memory chips= 1K X 32/ 1K X 8 =4

And no. of address lines to access= 1K X 8=1024= 2n = 10
Cache Memory
The basic idea of cache organisation is that by keeping the frequently used instructions
and data in cache memory the average memory access time will decrease
tremendously as it approaches the access time of cache memory.
Definition- A cache memory is a small high speed memory placed between the CPU
and the main memory.
• Even though cache is only a fraction of the size of the main memory, a large
fraction of memory request will be found in the cache memory because of the
property of locality of references in the program.
• When the CPU accesses memory, the cache is examined first. If the required
information is not found, then the main memory gets read. Then the information
is transferred to cache memory if it is frequently required.
• The performance of cache memory is measured in terms of Hit ratio.
• Hit- when CPU refers to the memory and finds the word in the cache, it is said to
be a hit.
• Miss- If the word is not found in the cache, it is said to be a miss.
• The Hit Ratio of the cache memory is the ratio of the number of hits to the total
number of references to the memory ( i.e. hit + miss)

if h is the hit ratio, tc is the cache access time, and tm is the access time of main
memory, then the effective access memory time is –

teff = h. tc+ (1-h)( tc+ tm)

Example-
Let tc = 100 nanoseconds, tm =600 nanoseconds. What is the effective access time if h
is 90% ?
→ here, teff = 0.9 x 100 x 10-9 +(1-0.9)( 100 x 10-9 + 600 x 10-9 )
Therefore teff = 160 x 10-9 i.e 160 nanoseconds.
Virtual memory
Virtual memory is a concept that is used in large computer systems that permits the
user to run the programs with a large memory space available equal to the totality of
the auxiliary memory.
This gives an illusion to the user that unlimited amount of physical memory is available
even though a limited amount of memory is present.

Explanation
In this, the active segments of the program are kept in high speed main memory and
moving the inactive segments back to auxiliary memory. This is done by the operating
system and the process is transparent to the user.
Definitions-
• Each address that is referenced by the CPU is called virtual address and the
memory space defined by such virtual address is called as address space.
• The actual address of the main memory is called the physical address and the
memory space defined by such physical address is called memory space.

Each address referenced by the CPU goes through an address mapping from virtual
address to a physical address the translation is done by a mapping table maybe stored
in a separate memory or the main memory itself.

Virtual memory management

Management of the virtual memory is done using one of the following ways-
1. Paging technique
2. Segmentation

Paging- In paging method, the address space and memory space are divided into
groups of fixed size called as blocks and page refers to a group of address space of the
same size as a block.

Example
The page size is 512 words, the size of main memory is 4K words, and the size of
auxiliary memory is 64K words. How many pages and blocks will be present.

➔ No of blocks= main memory / block size

=4K/512
= 4 x 1024 / 512
=8 blocks
No of pages = auxiliary memory / block size
= 64 x 1024/ 512
=128 pages