Design of Combinational Logic Circuits

Dr. Anand S.

Professor
Centre for Nanotechnology Research (CNR)
Vellore Institute of Technology, Vellore

anand.st@vit.ac.in 1
Combinational Circuits

• Digital Logic Circuits may be combinational or sequential.

• A combinational circuit consists of ‘n’ input variables, logic gates, and ‘m’ output variables.
• The outputs of the combinational circuits are determined by the present combinations of
the
input variables.
• Adders, multipliers, comparators,multiplexers, demultiplexers,encoders,decoders are few
examples of combinational circuits.

Block diagram of combinational circuit

Design Procedure of Combinational Circuits

• Design of combinational circuit starts from the specification of the design and culminates
to a
set of Boolean functions from which the logic diagram can be obtained.
• In general we have to do the following steps to design a combinational circuit
i. From the specification determine the required inputs and outputs and assign a
symbol
to each inputs and outputs.
ii. Derive the truth table that defines the relation between the inputs and the outputs.
iii. Obtain the simplified Boolean function for each output as a function of input
variables.
iv. Draw the logic circuit.
Converting the expression into
SOP:
Design of Half Adder

• A combinational circuit that performs the addition of two bits is called a half
adder.
• The two bit binary inputs are given the symbols x and y
• The two outputs are sum and carry with the symbols S and C respectively.

Block diagram of Half Truth Table of Half

Adder Adder
S = x’y + xy’ = x ⊕ y
C = xy
Implementation of Half-Adder

S = x’y + xy’ = x ⊕ y
C = xy
Design of Full Adder

• A combinational circuit that performs the addition of three binary bits (two binary
bits and
a previous carry) is called a full adder.
• The three binary inputs are given the symbols x , y and z
• The two outputs are sum and carry with the symbols S and C respectively.

Block diagram of Full Adder

Truth Table of Full Adder

K-Maps for Full Adder
Implementation of Full Adder

Full-adder can be implemented with two half adders and one OR gate. Dotted block
in the
below circuit indicates a half adder.
S = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
C = z(x ⊕ y) + xy = z(xy’ + x’y) + xy = xy’z + x’yz + xy
Design of Half Subtractor

• A combinational circuit that performs the subtraction of two bits is called a half
subtractor.
• The two bit binary inputs are given the symbols x and y
• The two outputs are Difference and Borrow with the symbols D and B respectively.

Block diagram of Half

Subtractor Truth Table of Half Subtractor

D = x’y + xy’ = x ⊕ y
B = x’y
Implementation of Half Subtractor

D = x’y + xy’ = x ⊕ y
B = x’y
Design of Full Subtractor

• A combinational circuit that performs the subtraction of three binary bits (two
binary bits
and a previous borrow) is called a full subtractor.
• The three binary inputs are given the symbols x , y and z
• The two outputs are difference and borrow with the symbols D and B
respectively.

Block diagram of Full Subtractor

D = x’y’z + x’yz’ + xy’z’ +
xyz B = x’y’z + x’yz’ + Truth Table of Full Subtractor
x’yz + xyz
K-Maps for Full Subtractor

D = x’y’z + x’yz’ + xy’z’ + xyz

B = x’y’z + x’yz’ + x’yz + xyz = x’z +
x’y+yz
K-map for K-map for
D B
Implementation of Full Subtractor
D = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
B = x’ (y ⊕ z) + yz = x’(y’z + yz’) + yz = x’y’z + x’yz’ + x’yz + xyz = x’z + x’y+yz

X Y Z

X’

Z
Multiplexers (Data Selectors)

It allows digital information from several sources to be routed onto a single line for transmission
over that line to a common destination. Thus it has several input lines and one output line.

4-data input MUX

• Multiplexer
• 2n data inputs
• n selection inputs
• 1 single output

• Selection input
determines the
input that should
be connected to
the output
4-data input MUX implementation
Example chip: 8-to-1 MUX
16 to 1 Multiplexing using 8 bit MUX (74HC151)

50
Implementing Boolean Functions using Mux

• Boolean Function of n variables can be implemented using a mux with n-1

selection input.

• First n-1 variables of the function is connected to the selection inputs of the
multiplexer.

• Left out variable is used for the data inputs.

Implementing Boolean Functions using Mux

• F(x,y,z) = Ʃ(1,2,6,7)
• x and y are connected to the selection inputs of the multiplexer in the same
order.
• x is connected to S1 and y is connected to S0
• z, z’, 0 and 1 are connected to the data inputs of the multiplexer
De-Multiplexer

• De-Mux is a combinational circuit that receives input from a single line and directs it to
one of the 2n output lines based on the ‘n’ bit selection lines.

• A decoder with enable input can function as a de-multiplexer with the following
considerations.

• The input of decoder can be considered as selection lines of the de-multiplexer

• The enable signal of the decoder can be considered as the data input of the de-
multiplexer
DLD - Module 4 - Combinational
Circuits
MUX and DE-MUX
Applications
Reference